W66910CD Winbond Electronics, W66910CD Datasheet - Page 53

• Manufacturer Part Number: W66910CD
• Manufacturer: Winbond Electronics

Specifications of W66910CD

• Lead Free Status / Rohs Status: Not Compliant

TMD Timer 2 Mode
1: Cyclic timer mode. The timer starts when it is written a non-zero count value and counts cyclically (periodically) with the
count value.
In both cases, a maskable interrupt TIN2 is generated every time the timer reaches zero. When timer starts, pin TOUT2 changes
to HIGH and toggles every half count time. Therefore, the period of TOUT2 equals count value.
In both cases, timer counts with the new value if it is written again before expiration.
The timer is stopped when it expires (TMD=0), or by writting zero count value (TMD=0 or 1).
TIDLE TOUT2 Idle
This bit defines value of TOUT2 pin when timer if off.
TCN5-0 Timer 2 Count Value
0: Timer is off.
1-63: Timer count value in unit of ms.
8.1.21 Layer 1_Ready Code L1_RC Read/Write Address 14H
Value after reset: 0CH
RC3-0 Ready Code
Activation Indication) by user. For example: Siemens PEB2091: AI=1100, Motorola MC145572: AI=1100.
8.1.22 Control Register
Value after reset : 00H
SRST Software Reset
When this bit is set to "1", a software reset signal is activated. The effects of this reset signal are equivalent to the hardware reset
pin , except that it does not affect the 8-bit microprocessor interface circuit. Register can be read/written when SRST=1.
This bit is not auto-clear, the software must write "0" to this bit to exit from the reset mode.
0: One shot count down mode. The timer starts when it is written a non-zero count value and stops when it reaches zero.
When GCI bus is being enabled, these four programmable bits are allowed to program different Layer 1_Ready Code (AI:
7
0
7
0
6
0
6
0
SRST
5
0
5
CTL Read/Write Address 15H
4
0
4
0
RC3
3
3
0
RC2
2
2
0
-53 -
OPS1
RC1
1
1
OPS0
RC0
0
0
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Data Sheet
Revision 1.0
Feb,2001