PEB20571FV3.1XT Infineon Technologies, PEB20571FV3.1XT Datasheet - Page 81
PEB20571FV3.1XT
Manufacturer Part Number
PEB20571FV3.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB20571FV3.1XT.pdf
(308 pages)
Specifications of PEB20571FV3.1XT
Lead Free Status / Rohs Status
Compliant
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3.4
The µP interface may be operated in different modes. This chapter describes how to
configure the DELIC to each mode.
3.4.1
The processor mode is selected by the MODE input pin of the DELIC. "Low" level selects
Infineon/ INTEL mode, "HIGH" level selects Motorola mode.
3.4.2
In both modes, the A-bus and the D-bus are used in parallel. The A-bus should be
connected to the 8 LSBs of AD-bus, coming from the µP, also in multiplexed mode. The
mode is determined according to the ALE input pin. When ALE is permanently driven to
‘1’, the DELIC works in de-multiplexed mode. Otherwise the DELIC works in multiplexed
mode.
The next figure describes the connection of the DELIC to the address and data buses in
the different modes.
Note: Motorola mode is used only with de-multiplexed AD bus. Intel/Infineon mode may
Data Sheet
be used with both, multiplexed or de-multiplexed AD bus.
µP Interface
Intel/Infineon or Motorola Mode
De-Multiplexed or Multiplexed Mode
64
Interface Description
PEB 20570
PEB 20571
2003-07-31
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