GWIXP455BAC Intel, GWIXP455BAC Datasheet - Page 36

• Manufacturer Part Number: GWIXP455BAC
• Manufacturer: Intel

Specifications of GWIXP455BAC

• Core Operating Frequency: 400MHz
• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Package Type: BGA
• Pin Count: 544
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Functional Overview
3.2.4
3.2.5
May 2005
36
The IMMU then continues the instruction pre-fetch by using the address translation just entered
into the ITLB. When an instruction pre-fetch hits in the ITLB, the IMMU continues the pre-fetch
using the address translation already resident in the ITLB.
Access permissions for each of up to 16 memory domains can be programmed. When an
instruction pre-fetch is attempted to an area of memory in violation of access permissions, the
attempt is aborted and a pre-fetch abort is sent to the core for exception processing. The IMMU and
DMMU can be enabled or disabled together.
Data Memory Management Unit
For data fetches, the Data Memory Management Unit (DMMU) controls logical-to-physical
address translation, memory-access permissions, memory-domain identifications, and attributes
(governing operation of the data cache or mini-data cache and write buffer). The DMMU contains
a 32-entry, fully associative data-translation, look-aside buffer (DTLB) that has a round-robin
replacement policy. DTLB entries 0 through 30 can be locked.
When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk mechanism
that fetches an associated descriptor from memory and loads it into the DTLB. The descriptor
contains information for logical-to-physical address translation, memory-access permissions,
memory-domain identifications, and attributes (governing operation of the D-cache or mini-data
cache and write buffer).
The DMMU continues the data fetch by using the address translation just entered into the DTLB.
When a data fetch hits in the DTLB, the DMMU continues the fetch using the address translation
already resident in the DTLB.
Access permissions for each of up to 16 memory domains can be programmed. When a data fetch
is attempted to an area of memory in violation of access permissions, the attempt is aborted and a
data abort is sent to the core for exception processing.
The IMMU and DMMU can be enabled or disabled together.
Instruction Cache
The Instruction Cache (I-Cache) can contain high-use, multiple-code segments or entire programs,
allowing the core access to instructions at core frequencies. This prevents core stalls caused by
multi-cycle accesses to external memory.
The 32-Kbyte I-cache is 32-set/32-way associative, where each set contains 32 ways and each way
contains a tag address, a cache line of instructions (eight 32-bit words and one parity bit per word),
and a line-valid bit. For each of the 32 sets, 0 through 28 ways can be locked. Unlocked ways are
replaceable via a round-robin policy.
The I-cache can be enabled or disabled. Attribute bits within the descriptors — contained in the
ITLB of the IMMU — provide some control over an enabled I-cache.
When a needed line (eight 32-bit words) is not present in the I-cache, the line is fetched (critical
word first) from memory via a two-level, deep-fetch queue. The fetch queue allows the next
instruction to be accessed from the I-cache, but only when its data operands do not depend on the
execution results of the instruction being fetched via the queue.
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-002