MT45W1ML16PAFA-70 WT Micron Technology Inc, MT45W1ML16PAFA-70 WT Datasheet - Page 10

• Manufacturer Part Number: MT45W1ML16PAFA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W1ML16PAFA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Partial Array Refresh (CR[2:0])
Default = Full Array Refresh
of the total memory array. This feature allows the sys-
tem to reduce current by only refreshing that part of
the memory array required by the host system. The
refresh options are full array, three-quarters array, one-
half array, one-quarter array, or none of the array. The
mapping of these partitions can start at either the
beginning or the end of the address map (see Tables 5
and 6 on page 11).
Sleep Mode (CR[4])
Default = PAR Enabled, DPD Disabled
mode is to be entered when ZZ# is driven LOW. If CR[4]
= 1, PAR operation is enabled. If CR[4] = 0, DPD opera-
tion is enabled. PAR can also be enabled directly by
writing to the CR using the software access sequence.
Note that this then disables ZZ# initiation of PAR. DPD
cannot be enabled or disabled using the software
access sequence; this should only be done using ZZ# to
access the CR.
This mode will be used when the system does not
require the storage provided by the CellularRAM
device. Any stored data will become corrupted when
DPD is enabled. When refresh activity has been re-
enabled, the CellularRAM device will require 150µs to
perform an initialization procedure before normal
operation can resume. DPD should not be enabled
using CR software access.
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
The PAR bits restrict refresh operation to a portion
The sleep mode bit determines which low-power
DPD operation disables all refresh-related activity.
ASYNC/PAGE CellularRAM MEMORY
10
Temperature Compensated Refresh (CR[6:5])
Default = On-Chip Temperature Sensor
perature sensor that automatically adjusts the refresh
rate according to the operating temperature. The on-
chip TCR is enabled by clearing both of the TCR bits in
the refresh configuration register (CR[6:5] = 00b). Any
other TCR setting enables a fixed refresh rate. When
the on-chip temperature sensor is enabled, the device
continually adjusts the refresh rate according to the
operating temperature.
refresh at three different temperature thresholds
(+15°C, +45°C, and +85°C). The setting selected must
be for a temperature higher than the case tempera-
ture of the CellularRAM device. If the case tempera-
ture is +35°C, the system can minimize self refresh
current consumption by selecting the +45°C setting.
The +15°C setting would result in inadequate
refreshing and cause data corruption.
Page Mode READ Operation (CR[7])
Default = Disabled
page mode READ operations are enabled. In the
power-up default state, page mode is disabled.
This CellularRAM device includes an on-chip tem-
The TCR bits also allow for adequate fixed-rate
The page mode operation bit determines whether
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2 MEG x 16, 1 MEG x 16
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