MT45W1ML16PAFA-70 WT Micron Technology Inc, MT45W1ML16PAFA-70 WT Datasheet - Page 5

• Manufacturer Part Number: MT45W1ML16PAFA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W1ML16PAFA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
MT45W1Mx16PA device are high-density alternatives to
SRAM and Pseudo SRAM products, popular in low-
power, portable applications. The MT45W2Mx16PA
contains 33,554,432 bits organized as 2,097,152
addresses by 16 bits.The MT45W1Mx16PA contains
16,777,216 bits organized as 1,048,576 addresses by 16
bits. These devices include the industry-standard, asyn-
chronous memory interface found on other low-power
SRAM or Pseudo SRAM offerings. Page mode accesses
are also included as a bandwidth-enhancing extension
to the asynchronous read protocol.
Power-Up Initialization
sensor that is used to launch the power-up initializa-
tion process. Initialization will load the CR with its
default setting. V
taneously, and when they reach a stable level above
1.70V, the device will require 150µs to complete its self-
initialization process (see Figure 3 below). During the
initialization period, CE# should remain HIGH. When
initialization is complete, the device is ready for nor-
mal operation.
Bus Operating Modes
CellularRAM products incorporate the industry-stan-
dard, asynchronous interface found on other low-
power SRAM or Pseudo SRAM offerings. This bus
interface supports asynchronous READ and WRITE
operations as well as the bandwidth-enhancing page
mode READ operation. The specific interface that is
supported is defined by the value loaded into the CR.
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
VccQ
In general, the MT45W2Mx16PA device and the
CellularRAM products include an on-chip voltage
The MT45W2Mx16PA and the MT45W1Mx16PA
Vcc
Figure 3: Power-Up Initialization
Vcc = 1.7V
CC
Device Initialization
and V
Timing
t
PU >
CC
150µs
Q must be applied simul-
Device ready for
normal operation
ASYNC/PAGE CellularRAM MEMORY
5
Asynchronous Mode
nous operating mode. This mode uses the industry-
standard SRAM control interface (CE#, OE#, WE#, LB#/
UB#). READ operations (Figure 4) are initiated by
bringing CE#, OE#, and LB#/UB# LOW while keeping
WE# HIGH. Valid data will be driven out of the I/Os
after the specified access time has elapsed. WRITE
operations (Figure 5) occur when CE#, WE#, and LB#/
UB# are driven LOW. During WRITE operations, the
level of OE# is a “Don't Care”; WE# will override OE#.
The data to be written will be latched on the rising edge
of CE#, WE#, or LB#/UB# (whichever occurs first).
ADDRESS
LB#/UB#
ADDRESS
CellularRAM products power up in the asynchro-
LB#/UB#
DATA
WE#
DATA
OE#
CE#
WE#
OE#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CE#
Figure 5: WRITE Operation
Figure 4: READ Operation
2 MEG x 16, 1 MEG x 16
t
t
WC = WRITE Cycle Time
RC = READ Cycle Time
ADDRESS VALID
ADDRESS VALID
©2004 Micron Technology, Inc. All Rights Reserved.
DATA VALID
DATA VALID
ADVANCE
DON’T CARE
DON’T CARE