MT45W1ML16PAFA-70 WT Micron Technology Inc, MT45W1ML16PAFA-70 WT Datasheet - Page 6

• Manufacturer Part Number: MT45W1ML16PAFA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W1ML16PAFA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Page Mode READ Operation
to the legacy asynchronous READ operation. In page-
mode-capable products, an initial asynchronous read
access is performed, then adjacent addresses can be
quickly read by simply changing the low-order
address. Addresses A[3:0] are used to determine the
members of the 16-address CellularRAM page.
Addresses A[4] and higher must remain fixed during
the entire page mode access. Figure 6 shows the timing
diagram for a page mode access.
addresses can be read in a shorter period of time than
random addresses. WRITE operations do not include
comparable page mode functionality.
LB#/UB# Operation
enable signals allow for byte-wide data transfers. Dur-
ing READ operations, enabled bytes are driven onto
the DQs. The DQs associated with a disabled byte are
put into a High-Z state during a READ operation. Dur-
ing WRITE operations, any disabled bytes will not be
transferred to the memory array and the internal value
will remain unchanged. During a WRITE cycle, the
data to be written is latched on the rising edge of CE#,
WE#, LB#, or UB#, whichever occurs first.
during an operation, the device will disable the data
bus from receiving or transmitting data. Although the
device will seem to be deselected, the device remains
in an active mode as long as CE# remains LOW.
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
ADDRESS
LB#/UB#
Page mode is a performance-enhancing extension
Page mode takes advantage of the fact that adjacent
The lower byte (LB#) enable and upper byte (UB#)
When both the LB# and UB# are disabled (HIGH)
DATA
WE#
OE#
CE#
Figure 6: Page READ Operation
Add[0]
t
AA
D[0]
t
Add[1]
APA
D[1]
t
Add[2]
APA
D[2]
t
Add[3]
APA
D[3]
DON’T CARE
ASYNC/PAGE CellularRAM MEMORY
6
Low Power Operation
Standby Mode Operation
reduced to the level necessary to perform the DRAM
refresh operation on the full array. Standby operation
occurs when CE# and ZZ# are HIGH.
READ and WRITE operations where the address and
control inputs remain static for an extended period of
time. This mode will continue until a change occurs to
the address or control inputs.
Temperature Compensated Refresh
adequate refresh at different temperatures. This
sensor. When the sensor is enabled, it continually
adjusts the refresh rate according to the operating
temperature. The on-chip sensor is enabled by default.
sponding to temperature thresholds of +15°C, +45°C,
and +85°C. The setting selected must be for a tempera-
ture higher than the case temperature of the Cellular-
RAM device. If the case temperature is +35°C, the
system can minimize self-refresh current consump-
tion by selecting the +45°C setting. The +15°C setting
would result in inadequate refreshing and cause data
corruption.
Partial Array Refresh
to a portion of the total memory array. This feature
enables the system to reduce refresh current by only
refreshing that part of the memory array that is abso-
lutely necessary. The refresh options are full array,
three-quarters array, one-half array, one-quarter array,
or none of the array. Data stored in addresses not
receiving refresh will become corrupted. The mapping
of these partitions can start at either the beginning or
the end of the address map (Tables 5 and 6 on
page 11). READ and WRITE operations are ignored
during PAR operation.
the CR has been set HIGH (CR[4] = 1). PAR can be initi-
ated by bring the ZZ# pin to the LOW state for longer
than 10µs. Returning ZZ# to HIGH will cause an exit
from PAR and the entire array will be immediately
available for READ and WRITE operations.
ware access sequence (see Software Access to the Con-
figuration Register on page 8). PAR is enabled
CellularRAM device includes an on-chip temperature
During standby, the device current consumption is
The device will enter a reduced power state during
Temperature compensated refresh (TCR) allows for
Three fixed refresh rates are also available, corre-
Partial array refresh (PAR) restricts refresh operation
The device only enters PAR mode if the SLEEP bit in
Alternatively, PAR can be initiated using the CR soft-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2 MEG x 16, 1 MEG x 16
©2004 Micron Technology, Inc. All Rights Reserved.
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