MT45W1ML16PAFA-70 WT Micron Technology Inc, MT45W1ML16PAFA-70 WT Datasheet - Page 11

• Manufacturer Part Number: MT45W1ML16PAFA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W1ML16PAFA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Table 4:
Table 5:
Table 6:
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
CR[2]
CR[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CR[7]
0
1
CR[6] CR[5]
CR[1]
1
0
1
Configuration Register Bit Mapping
0
32Mb Address Patterns for PAR (CR[4] = 1)
CR[1]
16Mb Address Patterns for PAR (CR[4] = 1)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
All must be set to "0"
Page Mode Disabled (default)
Page Mode Enabled
1
0
1
0
Page Mode Enable/Disable
RESERVED
+15˚C
+85˚C
Internal sensor (default)
+45˚C
Maximum Case Temp.
A[20:8]
20– 8
CR[0]
CR[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Three-quarters of die
Three-quarters of die
Three-quarters of die
Three-quarters of die
One-quarter of die
One-quarter of die
One-quarter of die
One-quarter of die
ACTIVE SECTION
ACTIVE SECTION
PAGE
One-half of die
One-half of die
One-half of die
One-half of die
None of die
None of die
7
A7
Full die
Full die
6
TCR
A6
5
A5
SLEEP
CR[4]
ASYNC/PAGE CellularRAM MEMORY
0
1
4
A4
11
Must be set to "0"
ADDRESS SPACE
ADDRESS SPACE
RESERVED
000000h–1FFFFFh
000000h–2FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
100000h–3FFFFFh
200000h–3FFFFFh
300000h–3FFFFFh
DPD Enabled
PAR Enabled (default)
00000h–BFFFFh
00000h–7FFFFh
00000h–3FFFFh
C0000h–FFFFFh
00000h–FFFFFh
40000h–FFFFFh
80000h–FFFFFh
3
A3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Sleep Mode
0
0
CR[2]
2
0
0
0
0
1
1
1
1
A2
2 MEG x 16, 1 MEG x 16
CR[1]
0
0
1
1
0
0
1
1
PAR
CR[0]
1
A1
1
0
1
0
1
0
0
1
1.5 Meg x 16
1.5 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
1 Meg x 16
1 Meg x 16
0 Meg x 16
512K x 16
512K x 16
768K x 16
512K x 16
256K x 16
768K x 16
512K x 16
256K x 16
Full array (default)
Bottom 3/4 array
Bottom 1/4 array
None of array
Top 3/4 array
Top 1/4 array
Bottom 1/2 array
Top 1/2 array
SIZE
SIZE
PAR Refresh Coverage
©2004 Micron Technology, Inc. All Rights Reserved.
0
A0
Configuration
Address Bus
Register
ADVANCE
DENSITY
DENSITY
32Mb
24Mb
16Mb
24Mb
16Mb
16Mb
12Mb
12Mb
8Mb
0Mb
8Mb
8Mb
4Mb
0Mb
8Mb
4Mb