EVAL-ADV7311EB Analog Devices Inc, EVAL-ADV7311EB Datasheet - Page 18

• Manufacturer Part Number: EVAL-ADV7311EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADV7311EB

• Lead Free Status / Rohs Status: Not Compliant

ADV7310/ADV7311
SR7–
SR0
00h
01h
Register
Power Mode
Register
Mode Select
Register
Sleep Mode. With this
control enabled, the
current consumption is
reduced to µA level. All
DACs and the internal
PLL cct are disabled. I
registers can be read from
and written to in Sleep
Mode.
PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the over-sampling to be
switched off.
Bit Description
DAC F: Power On/Off
DAC E: Power On/Off
DAC D: Power On/Off
DAC C: Power On/Off
DAC B: Power On/Off
DAC A: Power On/Off
BTA T-1004 or BT.1362
Compatibility
Clock Edge
Reserved
Clock Align
Input Mode
Y/S Bus Swap
2
C
Bit 7 Bit 6 Bit 5
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
Bit 4 Bit 3 Bit 2 Bit 1
0
1
0
1
0
1
0
1
0
1
–18–
0
1
0
1
0
1
0
0
1
0
1
Bit 0 Register Setting
0
1
0
1
Sleep Mode off
Sleep Mode on
PLL on
PLL off
DAC F off
DAC F on
DAC E off
DAC E on
DAC D off
DAC D on
DAC D off
DAC C on
DAC B off
DAC B on
DAC A off
DAC A on
Disabled
Enabled
Cb clocked on rising edge
Y clocked on rising edge
Must be set if the phase
delay between the two input
clocks is <9.25 ns or
>27.75 ns.
SD input only
PS input only
HDTV input only
SD and PS [20-bit]
SD and PS [10-bit]
SD and HDTV [SD
oversampled]
SD and HDTV [HDTV
oversampled]
PS only [at 54 MHz]
10-bit data on S bus
10-bit data on Y bus
Register Reset Values
(Shaded)
FCh
Only for PS dual edge clk mode
Only for PS interleaved input at
27 MHz
Only if two input clocks are used
38h
SD Mode 10-bit/20-bit Modes
REV. A