EVAL-ADV7311EB Analog Devices Inc, EVAL-ADV7311EB Datasheet - Page 72

• Manufacturer Part Number: EVAL-ADV7311EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADV7311EB

• Lead Free Status / Rohs Status: Not Compliant

ADV7310/ADV7311
Mode 3—Master/Slave Option
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7310/ADV7311 accept or generate horizon-
tal sync and odd/even field signals. A transition of the field input
when HSYNC is high indicates a new frame, i.e., vertical retrace.
The BLANK signal is optional. When the BLANK input is dis-
abled, the ADV7310/ADV7311 automatically blank all normally
blank lines as per CCIR-624. HSYNC is output in master mode
and input in slave mode on S_VSYNC, BLANK on S_BLANK,
and VSYNC on S_VSYNC.
HSYNC
BLANK
HSYNC
BLANK
FIELD
FIELD
HSYNC
BLANK
HSYNC
BLANK
FIELD
FIELD
522
260
DISPLAY
DISPLAY
523
261
622
309
DISPLAY
DISPLAY
524
262
623
310
263
525
624
311
EVEN FIELD
EVEN FIELD
264
ODD FIELD
1
625
312
265
EVEN FIELD
2
ODD FIELD
ODD FIELD
313
1
Figure 89. SD Timing Mode 3 (NTSC)
Figure 90. SD Timing Mode 3 (PAL)
EVEN FIELD
266
3
314
2
ODD FIELD
267
4
315
3
268
5
VERTICAL BLANK
VERTICAL BLANK
–72–
316
4
VERTICAL BLANK
VERTICAL BLANK
269
6
317
5
270
7
318
6
271
8
319
7
272
9
320
273
10
21
274
11
334
22
DISPLAY
335
283
23
20
DISPLAY
284
336
21
DISPLAY
285
DISPLAY
22
REV. A