EVAL-ADV7311EB Analog Devices Inc, EVAL-ADV7311EB Datasheet - Page 26

• Manufacturer Part Number: EVAL-ADV7311EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADV7311EB

• Lead Free Status / Rohs Status: Not Compliant

ADV7310/ADV7311
SR7–
SR0
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
Register
SD Timing
Register 0
SD Timing
Register 1
SD F
SD F
SD F
SD F
SD F
SD Closed
Captioning
SD Closed
Captioning
SD Closed
Captioning
SD Closed
Captioning
SD Pedestal
Register 0
SD Pedestal
Register 1
SD Pedestal
Register 2
SD Pedestal
Register 3
SC
SC
SC
SC
SC
Register 0
Register 1
Register 2
Register 3
Phase
Bit Description
SD Slave/Master Mode
SD Timing Mode
SD BLANK Input
SD Luma Delay
SD Min. Luma Value
SD Timing Reset
SD HSYNC Width
SD HSYNC to VSYNC delay
SD HSYNC to VSYNC Rising
Edge Delay [Mode 1 Only]
VSYNC Width [Mode 2 Only]
HSYNC to Pixel Data Adjust
Extended Data on Even Fields
Extended Data on Even Fields
Data on Odd Fields
Data on Odd Fields
Pedestal on Odd Fields
Pedestal on Odd Fields
Pedestal on Even Fields
Pedestal on Even Fields
HSYNC
VSYNC
t
LINE 1
B
Figure 21. Timing Register 1 in PAL Mode
t
A
Bit 7
x
0
0
1
1
x
x
x
x
x
x
x
x
x
17
25
17
25
Bit 6
0
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
16
24
16
24
Bit 5
0
0
1
1
0
x
x
0
0
1
1
x
x
x
x
x
x
x
x
x
15
23
15
23
–26–
Bit 4
0
1
0
1
0
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
14
22
14
22
Bit 3
0
1
0
0
0
1
1
x
x
x
x
x
x
x
x
x
13
21
13
21
Bit 2
0
0
1
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
12
20
12
20
t
C
LINE 313
Bit 1
0
1
0
1
0
0
0
1
1
x
x
x
x
x
x
x
x
x
11
19
11
19
Bit 0
0
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
10
18
10
18
LINE 314
Register Setting
Slave Mode
Master Mode
Mode 0
Mode 1
Mode 2
Mode 3
Enabled
Disabled
No delay
2 clk cycles
4 clk cycles
6 clk cycles
– 40 IRE
– 7.5 IRE
A low-high-low transition will reset
the internal SD timing counters
Ta = 1 clk cycle
Ta = 4 clk cycles
Ta = 16 clk cycles
Ta = 128 clk cycles
Tb = 0 clk cycle
Tb = 4 clk cycles
Tb = 8 clk cycles
Tb = 18 clk cycles
Tc = Tb
Tc = Tb + 32 us
1 clk cycle
4 clk cycles
16 clk cycles
128 clk cycles
0 clk cycles
1 clk cycle
2 clk cycles
3 clk cycles
Subcarrier Frequency Bit 7–0
Subcarrier Frequency Bit 15–8
Subcarrier Frequency Bit 23–16
Subcarrier Frequency Bit 31–24
Subcarrier Phase Bit 9–2
Extended Data Bit 7–0
Extended Data Bit 15–8
Data Bit 7–0
Data Bit 15–8
Setting any of these bits to 1 will
disable pedestal on the line number
indicated by the bit settings
REV. A
Reset
Values
08h
00h
16h
7Ch
F0h
21h
00h
00h
00h
00h
00h
00h
00h
00h
00h