LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 153

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
7.2
SYMBOL
t
t
t
t
cycle
t
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
nCS, nRD
ah
A[7:1]
Data Bus
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles
is identical with the exception that D[31:16] are not driven during a 16-bit read.
Note:
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
Some registers have restrictions on the timing of back-to-back, write-read and read-
read cycles.
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Figure 7.1 LAN9118 PIO Read Cycle Timing
Table 7.3 PIO Read Timing
DATASHEET
153
MIN
45
32
13
0
0
0
0
TYP
Revision 1.0 (03-17-05)
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns