LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 38

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
4.7
MODE OF
OPERATION
Mode 0 (Big Endian Register equal to 0xFFFFFFFF)h
Mode 1 (Big Endian Register not equal to 0xFFFFFFFF)h
A1 = 0
A1 = 1
A1 = 0
A1 = 1
The SMSC LAN9118 supports “Big-” or “Little-Endian” processors in either 16 or 32-bit bus width
modes. To support big-endian processors, the hardware designer must explicitly invert the layout of
the byte lanes. In addition, for a 16-bit interface, the big-endian register must be set correctly following
the table below
The host bus interface can be selected via an external strap to translate the data bus into either mode.
Please refer to
multiplexed signal D32/nD16 for more information on data bus width selection.
Additionally, please refer to
information on status indication on Endian modes.
Big and Little Endian Support
32-bit
D[31:24]
Byte 3
(MSB)
--
--
--
--
Table 2.4, “Serial EEPROM Interface Signals,” on page
D[23:16]
Byte 2
--
--
--
--
Table 4.7 Byte Lane Mapping
DATA PINS
Section 6.3.17, "ENDIAN—Endian Control," on page 108
DATASHEET
D[15:8]
Byte 1
Byte 3
Byte 1
Byte 1
Byte 3
38
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
D[7:0]
Byte 0
Byte 2
Byte 0
Byte 0
Byte 2
(LSB)
This is the native mode of the LAN9118.
Endianess does not matter when both
WORD lanes are in operation.
Note:
Note:
This mode can be used by 32-
bit processors operating with
an external 16-bit bus.
This mode can also be used by
native 16-bit processors.
DESCRIPTION
20, for information on
SMSC LAN9118
for additional
Datasheet