LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 85

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
6.3.2
IRQ_CFG—Interrupt Configuration Register
This register configures and indicates the state of the IRQ signal.
BITS
23-15
31:24
Offset:
11-9
7-5
3-1
14
13
12
8
4
DESCRIPTION
Interrupt Deassertion Interval (INT_DEAS). This field
determines the Interrupt Deassertion Interval for the
Interrupt Request in multiples of 10 microseconds.
Writing zeros to this field disables the INT_DEAS Interval
and resets the interval counter. Any pending interrupts are
then issued. If a new, non-zero value is written to the
INT_DEAS field, any subsequent interrupts will obey the
new setting.
NOTE: The Interrupt Deassertion interval does not apply to
the PME interrupt.
Reserved
Interrupt Deassertion Interval Clear (INT_DEAS_CLR).
Writing a one to this register clears the de-assertion counter
in the IRQ Controller, thus causing a new de-assertion
interval to begin (regardless of whether or not the IRQ
Controller is currently in an active de-assertion interval).
Interrupt Deassertion Status (INT_DEAS_STS).
this bit indicates that the INT_DEAS is currently in a deassertion
interval, and any interrupts (as indicated by the IRQ_INT and
INT_EN bits) will not be delivered to the IRQ pin. When cleared, the
INT_DEAS is currently not in a deassertion interval, and enabled
interrupts will be delivered to the IRQ pin.
Master Interrupt (IRQ_INT).
state of the internal IRQ line. When set high, one of the enabled
interrupts is currently active. This bit will respond to the associated
interrupts regardless of the IRQ_EN field. This bit is not affected by
the setting of the INT_DEAS field.
Reserved
IRQ Enable (IRQ_EN) –
output to the IRQ pin. When cleared, the IRQ output is disabled and
will be permanently deasserted. This bit only controls the external
IRQ signal, and has no effect on any of the internal interrupt status
bits.
Reserved
IRQ Polarity (IRQ_POL) –
to function as an active low output. When set, the IRQ output is
active high. When IRQ is configured as an open-drain output this
field is ignored, and the interrupt output is always active low.
Reserved
54h
DATASHEET
This bit controls the final interrupt
When cleared, enables the IRQ line
85
This read-only bit indicates the
Size:
When set,
32 bits
TYPE
NASR
R/W
R/W
R/W
RO
RO
RO
RO
RO
SC
Revision 1.0 (03-17-05)
DEFAULT
0
0
0
0
0
-
-
-
-