LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 50

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) after an internal
Revision 1.0 (03-17-05)
4.11
4.11.1
4.11.2
PHY REG 0.15
SOURCE
RESET
PHY_RST
nRESET
SRST
POR
The LAN9118 has five reset sources:
■
■
■
■
■
Table 4.10
Note 4.10 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic
Note 4.11 After a POR, nRESET or SRST, the LAN9118 will automatically check for the presence of
Note 4.12 HBI - “Host Bus Interface”, NASR - Not affected by software reset
Power-On Reset (POR)
A Power-On reset occurs whenever power is initially applied to the LAN9118, or if power is removed
and reapplied to the LAN9118. A timer within the LAN9118 will assert the internal reset for
approximately 22ms. The READY bit in the PMT_CTRL register can be read from the host interface
and will read back a ‘0’ until the POR is complete. Upon completion of the POR, the READY bit in
PMT_CTRL is set high, and the LAN9118 can be configured via its control registers.
Hardware Reset Input (nRESET)
A hardware reset will occur when the nRESET input signal is driven low. The READY bit in the
PMT_CTRL register can be read from the host interface, and will read back a ‘0’ until the hardware
reset is complete. Upon completion of the hardware reset, the READY bit in PMT_CTRL is set high.
Detailed Reset Description
Power-On Reset (POR)
Hardware Reset Input Pin (nRESET)
Soft Reset (SRST)
PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)
PHY Soft Reset via PHY Basic Control Register (PHY REG 0.15)
PLL
X
X
reset (22ms). If the software driver polls this bit and it is not set within 100ms, then an error
condition occurred.
shows the effect of the various reset sources on the LAN9118's circuitry.
Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data.
an external EEPROM. After any of these resets the application must verify that the EPC
Busy Bit (E2P_CMD, bit 31) is cleared before attempting to access the EEPROM, or
change the function of the GPO/GPIO signals, or before modifying the ADDRH or ADDRL
registers in the MAC.
Table 4.10 PHY Reset Sources and Effected Circuitry
Note
HBI
4.1
2
X
X
X
REGISTERS
Note 4.12
NASR
X
X
DATASHEET
MIL
X
X
X
50
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
MAC
X
X
X
Note 4.1
PHY
X
X
X
X
0
EEPROM MAC
RELOAD
Note 4.11
ADDR.
X
X
X
LATCHED
SMSC LAN9118
CONFIG.
STRAPS
X
X
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