LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 36

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
4.5.1
4.6
4.6.1
Magic Packet Detection
Setting the Magic Packet Enable bit (MPEN) in the “WUCSR—Wake-up Control and Status Register”,
places the LAN9118 MAC in the “Magic Packet” detection mode. In this mode, normal data reception
is disabled, and detection logic within the MAC examines receive data for a Magic Packet. The
LAN9118 can be programmed to notify the host of the “Magic Packet” detection with the assertion of
the host interrupt (IRQ) or assertion of the power managment event signal (PME). Upon detection, the
Magic Packet Received bit (MPR) in the WUCSR is set. When the host clears the MPEN bit the
LAN9118 will resume normal receive operation. Please refer to
Control and Status Register," on page 134
In Magic Packet mode, the Power Management Logic constantly monitors each frame addressed to
the node for a specific Magic Packet pattern. It checks only packets with the MAC’s address or a
broadcast address to meet the Magic Packet requirement. The Power Management Logic checks each
received frame for the pattern 48h FF_FF_FF_FF_FF_FF after the destination and source address
field.
Then the Function looks in the frame for 16 repetitions of the MAC address without any breaks or
interruptions. In case of a break in the 16 address repetitions, the PMT Function scans for the
48'hFF_FF_FF_FF_FF_FF pattern again in the incoming frame.
The 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream.
The device will also accept a multicast frame, as long as it detects the 16 duplications of the MAC
address. If the MAC address of a node is 00h 11h 22h 33h 44h 55h, then the MAC scans for the
following data sequence in an Ethernet: Frame.
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
It should be noted that Magic Packet detection can be performed when LAN9118 is in the D0 or D1
power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the
D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when
the device enters the D1 state.
The LAN9118 can be configured to communicate with the host bus via either a 32-bit or a 16-bit bus.
An external strap is used to select between the two modes. 32-bit mode is the native environment for
the LAN9118 Ethernet controller and no special requirements exist for communication in this mode.
However, when this part is used in the 16-bit mode, two writes or reads must be performed back to
back to properly communicate.
The bus width is set by strapping the EEDIO pin; this setting can be read from bit 2 of the “Hardware
Configuration Register”. Please refer to
on page 95
16-bit Bus Writes
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit write). No ordering requirements exist. The processor can access either
32-bit vs. 16-bit Host Bus Width Operation
for additional information on this register.
DATASHEET
Section 6.3.9, "HW_CFG—Hardware Configuration Register,"
36
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
for additional information on this register
Section 6.4.12, "WUCSR—Wake-up
SMSC LAN9118
Datasheet