DSPB56374AE Freescale Semiconductor, DSPB56374AE Datasheet - Page 32

• Manufacturer Part Number: DSPB56374AE
• Description: IC DSP 24BIT 150MHZ 52-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56374AE

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (84 kB)
• On-chip Ram: 54kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 150 MIPS
• Maximum Clock Frequency: 150 MHz
• Program Memory Type: Flash
• Program Memory Size: 24 KB
• Data Ram Size: 54 KB
• Operating Supply Voltage: 1.25 V or 3.3 V
• Maximum Operating Temperature: + 110 C
• Mounting Style: SMD/SMT
• Interface Type: SIA, SHI
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset, Stop, Mode Select, and Interrupt Timing
12
32
No.
10
11
13
14
15
16
17
18
19
20
Reset, Stop, Mode Select, and Interrupt Timing
Delay from RESET assertion to all pins at reset
value
Required RESET duration
Syn reset deassert delay time
Mode select setup time
Mode select hold time
Minimum edge-triggered interrupt request assertion
width
Minimum edge-triggered interrupt request
deassertion width
Delay from interrupt trigger to interrupt code
execution
Duration of level sensitive IRQA assertion to ensure
interrupt service (when exiting Stop)
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Minimum
• Maximum (PLL enabled)
• PLL is active during Stop and Stop delay is
• PLL is active during Stop and Stop delay is not
• PLL is not active during Stop and Stop delay is
• PLL is not active during Stop and Stop delay is
• Delay from IRQA, IRQB, IRQC, IRQD, NMI
3
enabled
(OMR Bit 6 = 0)
enabled
(OMR Bit 6 = 1)
enabled (OMR Bit 6 = 0)
not enabled (OMR Bit 6 = 1)
assertion to general-purpose transfer output
valid caused by first interrupt instruction
execution
1
Table 20. Reset, Stop, Mode Select, and Interrupt Timing
Characteristics
4
DSP56374 Data Sheet, Rev. 4.2
1, 2, 3
9+(128xT
(25 x T
(2xT
10 x T
Expression
9+(128× T
10 × T
25× T
2 x T
2× T
2 xT
2 xT
2 xT
C
C
)+T
—
C
) + T
C
C
) + T
C
C
C
+ 3.0
C
C
LOCK
+ 5
C
C
LOCK
)
LOCK
13.4
13.4
13.4
10.0
10.0
13.4
13.4
Min
854
165
5.0
5.7
—
72
5
Freescale Semiconductor
Max
69.0
11
—
—
—
—
—
—
—
—
—
—
—
Unit
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns