DSPB56374AE Freescale Semiconductor, DSPB56374AE Datasheet - Page 43

• Manufacturer Part Number: DSPB56374AE
• Description: IC DSP 24BIT 150MHZ 52-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56374AE

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (84 kB)
• On-chip Ram: 54kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 150 MIPS
• Maximum Clock Frequency: 150 MHz
• Program Memory Type: Flash
• Program Memory Size: 24 KB
• Data Ram Size: 54 KB
• Operating Supply Voltage: 1.25 V or 3.3 V
• Maximum Operating Temperature: + 110 C
• Mounting Style: SMD/SMT
• Interface Type: SIA, SHI
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15
The programmed serial clock cycle, T
HCKR (SHI clock control register).
The expression for T
In I
The programmed serial clock cycle (T
clock cycle (T
Freescale Semiconductor
2
C mode, the user may select a value for the programmed serial clock cycle from
Note:
No.
1
2
3
4
5
where
— HRS is the prescaler rate select bit. When HRS is cleared, the fixed
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00
to
V
Pull-up resistor: R
Capacitive load: C
All times assume noise free inputs
All times assume internal clock frequency of 150MHz
Programming the Serial Clock
CORE_VDD
divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.
to $FF) may be selected.
SCL
Characteristics
Nominal
), as shown in
= 1.2 5 ± 0.05 V; T
I
2
CCP
Table 23. SCL Serial Clock Cycle (T
T
P
b
I
2
(min) = 1.5 kOhm
(max) = 50 pF
CCP
is
4096 × T
= [T
Table 22. SHI I
6 × T
1,2,3,4,5
Table
C
J
= -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), C
C
× 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
C
(if HDM[7:0] = $02 and HRS = 1)
I
I
2
23.
CCP
(if HDM[7:0] = $FF and HRS = 0)
2
DSP56374 Data Sheet, Rev. 4.2
CCP
T
I
2
CCP
, is specified by the value of the HDM[7:0] and HRS bits of the
) should be chosen in order to achieve the desired SCL serial
2
C Protocol Timing (continued)
+ 3 × T
Standard I
Expression
Symbol/
C
+ 45ns + T
2
C
SCL
) Generated as Master
Min
R
Standard
Max
Programming the Serial Clock
Min
Fast-Mode
L
= 50 pF
Max
Unit
Eqn. 1
Eqn. 2
Eqn. 3
43