DSPB56374AE Freescale Semiconductor, DSPB56374AE Datasheet - Page 46

• Manufacturer Part Number: DSPB56374AE
• Description: IC DSP 24BIT 150MHZ 52-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56374AE

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (84 kB)
• On-chip Ram: 54kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 150 MIPS
• Maximum Clock Frequency: 150 MHz
• Program Memory Type: Flash
• Program Memory Size: 24 KB
• Data Ram Size: 54 KB
• Operating Supply Voltage: 1.25 V or 3.3 V
• Maximum Operating Temperature: + 110 C
• Mounting Style: SMD/SMT
• Interface Type: SIA, SHI
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Serial Audio Interface Timing
46
Note:
No.
88
89
90
91
92
93
94
95
96
97
1
2
3
4
5
6
7
8
V
i ck = internal clock
bl = bit length
SCKT(SCKT pin) = transmit clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame
Periodically sampled and not 100% tested.
ESAI_1 specs match those of ESAI.
x ck = external clock
i ck a = internal clock, asynchronous mode
i ck s = internal clock, synchronous mode
wl = word length
wr = word length relative
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until
the one before last bit clock of the first word in frame.
(asynchronous implies that SCKT and SCKR are two different clocks)
(synchronous implies that SCKT and SCKR are the same clock)
CORE_VDD
SCKT edge to transmitter #0 drive enable
deassertion
FST input (bl, wr) setup time before SCKT
edge
FST input (wl) setup time before SCKT
edge
FST input hold time after SCKT edge
FST input (wl) to data out enable from high
impedance
FST input (wl) to transmitter #0 drive enable
assertion
Flag output valid after SCKT rising edge
HCKR/HCKT clock cycle
HCKT input edge to SCKT output
HCKR input edge to SCKR output
6
= 1.25 ± 0.05 V; T
Characteristics
7
Table 24. Enhanced Serial Audio Interface Timing (continued)
1, 2, 3
J
= -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), C
DSP56374 Data Sheet, Rev. 4.2
Symbol
—
—
—
—
—
—
—
—
—
—
Expression
2 x T
—
—
—
—
—
—
—
—
—
C
3
18.0
18.0
13.4
Min
2.0
2.0
4.0
5.0
—
—
—
—
—
—
—
—
Max
14.0
21.0
14.0
14.0
18.0
18.0
9.0
9.0
—
—
—
—
—
—
—
L
= 50 pF
Freescale Semiconductor
Condition
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
—
—
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns