EP2C5Q208C7N Altera, EP2C5Q208C7N Datasheet - Page 17

• Manufacturer Part Number: EP2C5Q208C7N
• Description: IC CYCLONE II FPGA 5K 208-PQFP
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C5Q208C7N

• Number Of Logic Elements/cells: 4608
• Number Of Labs/clbs: 288
• Total Ram Bits: 119808
• Number Of I /o: 142
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 4608
• # I/os (max): 142
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 4608
• Ram Bits: 119808
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1674

Figure 2–3. LE in Normal Mode
Altera Corporation
February 2007
data1
data2
data3
cin (from cout
of previous LE)
data4
Packed Register Input
Register Feedback
Four-Input
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters,
accumulators, and comparators. An LE in arithmetic mode implements a
2-bit full adder and basic carry chain (see
mode can drive out registered and unregistered versions of the LUT
output. Register feedback and register packing are supported when LEs
are used in arithmetic mode.
LUT
Register chain
connection
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
(LAB Wide)
sclear
Cyclone II Device Handbook, Volume 1
ENA
D
CLRN
Figure
Q
2–4). LEs in arithmetic
Cyclone II Architecture
Row, Column, and
Direct Link Routing
Row, Column, and
Direct Link Routing
Local routing
Register
chain output
2–5