EP2C5Q208C7N Altera, EP2C5Q208C7N Datasheet - Page 37

IC CYCLONE II FPGA 5K 208-PQFP

EP2C5Q208C7N

Manufacturer Part Number
EP2C5Q208C7N
Description
IC CYCLONE II FPGA 5K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C5Q208C7N

Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
142
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
4608
# I/os (max)
142
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
4608
Ram Bits
119808
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1674

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2C5Q208C7N
Manufacturer:
ALTERA
Quantity:
45
Part Number:
EP2C5Q208C7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2C5Q208C7N
Manufacturer:
ALTERA
0
Part Number:
EP2C5Q208C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
February 2007
PLLs
Cyclone II PLLs provide general-purpose clocking as well as support for
the following features:
Cyclone II devices contain either two or four PLLs.
PLLs available for each Cyclone II device.
EP2C5
EP2C8
EP2C15
EP2C20
EP2C35
EP2C50
EP2C70
Table 2–3. Cyclone II Device PLL Availability
Device
Clock multiplication and division
Phase shifting
Programmable duty cycle
Up to three internal clock outputs
One dedicated external clock output
Clock outputs for differential I/O support
Manual clock switchover
Gated lock signal
Three different clock feedback modes
Control signals
PLL1
v
v
v
v
v
v
v
PLL2
Cyclone II Device Handbook, Volume 1
v
v
v
v
v
v
v
PLL3
v
v
v
v
v
Cyclone II Architecture
Table 2–3
shows the
PLL4
v
v
v
v
v
2–25

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