XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 46

IC FPGA VIRTEX-4 FX 60K 1152FBGA

XC4VFX60-10FFG1152C

Manufacturer Part Number
XC4VFX60-10FFG1152C
Description
IC FPGA VIRTEX-4 FX 60K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

Total Ram Bits
4276224
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Number Of I /o
576
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
No. Of Logic Blocks
6656
No. Of Macrocells
56880
Family Type
Virtex-4
No. Of Speed Grades
10
No. Of I/o's
576
Clock Management
DCM
Core Supply
RoHS Compliant
Package
1152FCBGA
Family Name
Virtex®-4
Device Logic Units
56880
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
576
Ram Bits
4276224
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
XILINX
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Part Number:
XC4VFX60-10FFG1152C
Quantity:
205
Part Number:
XC4VFX60-10FFG1152C
0
Virtex-4 FPGA Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in
Table 56: Global Clock Setup and Hold for LVCMOS25 Standard, with DCM
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.
T
PSDCM
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the
Global Clock input signal with the slowest route and heaviest load.
These measurements include:
CLK0 DCM jitter
IFF = Input Flip-Flop or Latch
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Symbol
Table
/
T
PHDCM
56. Values are expressed in nanoseconds unless otherwise noted.
No Delay Global Clock and IFF
Description
(2)
with DCM
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
XC4VFX100
XC4VFX140
XC4VLX100
XC4VLX160
XC4VLX200
XC4VSX25
XC4VSX35
XC4VSX55
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
Device
(1)
–0.72
–0.58
–0.55
–0.43
–0.26
–0.20
–0.20
–0.50
–0.41
–0.23
–0.71
–0.52
–0.18
–0.06
1.35
1.28
1.25
1.25
1.22
1.27
1.54
1.25
1.21
1.25
1.35
1.25
1.23
1.17
1.21
0.11
-12
N/A
N/A
Speed Grade
–0.67
–0.57
–0.50
–0.40
–0.21
–0.14
–0.13
–0.48
–0.38
–0.18
–0.69
–0.51
–0.13
1.52
1.50
1.44
1.47
1.42
1.48
1.79
1.90
0.03
1.47
1.43
1.47
1.55
1.48
1.45
1.37
0.01
1.42
0.20
1.68
0.21
-11
–0.62
–0.55
–0.46
–0.36
–0.15
–0.08
–0.05
–0.48
–0.34
–0.13
–0.69
–0.51
–0.08
1.54
1.58
1.50
1.55
1.49
1.56
1.89
2.00
0.15
1.55
1.50
1.55
1.61
1.56
1.52
1.44
0.09
1.49
0.31
1.76
0.31
-10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
46

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