CY8CTST200-32LQXI Cypress Semiconductor Corp, CY8CTST200-32LQXI Datasheet - Page 246

• Manufacturer Part Number: CY8CTST200-32LQXI
• Description: IC MCU 32K FLASH 32UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-32LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2957

INT_CLR2
21.3.56 INT_CLR2
This register is used to enable the individual interrupt sources' ability to clear posted interrupts.
When bits in this register are read, a '1' is returned for every bit position that has a corresponding posted interrupt. When bits
in this register are written with a '0' and ENSWINT is not set, posted interrupts are cleared at the corresponding bit positions.
If there is no posted interrupt, there is no effect. In the table above, note that reserved bits are grayed table cells and are not
described in the bit description section below. Reserved bits must always be written with a value of ‘0’. When bits in this reg-
ister are written with a '1' and ENSWINT is set, an interrupt is posted in the interrupt controller. For additional information,
refer to the
Bit
5
4
(continued on next page)
246
Individual Register Names and Addresses:
INT_CLR2 : 0,DCh
Access : RW:00
Bit Name
0,DCh
USB_WAKE
Endpoint8
Name
Register Definitions on page 48
Interrupt Clear Register 2
7
6
Description
Read 0 No posted interrupt for USB Wake.
Read 1 Posted interrupt present for USB Wake.
Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists.
Write 1 AND ENSWINT = 0 No effect.
Write 0 AND ENSWINT = 1 No effect.
Write 1 AND ENSWINT = 1 Post an interrupt for USB Wake.
Read 0 No posted interrupt for USB Endpoint8.
Read 1 Posted interrupt present for USB Endpoint8.
Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists.
Write 1 AND ENSWINT = 0 No effect.
Write 0 AND ENSWINT = 1 No effect.
Write 1 AND ENSWINT = 1
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
USB_WAKE
in the Interrupt Controller chapter.
RW : 0
5
0,DCh
Endpoint8
RW : 0
Post an interrupt for USB Endpoint8.
4
Endpoint7
RW : 0
3
Endpoint6
RW : 0
2
Endpoint5
RW : 0
1
Endpoint4
RW : 0
0
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