CY8CTST200-32LQXI Cypress Semiconductor Corp, CY8CTST200-32LQXI Datasheet - Page 284

• Manufacturer Part Number: CY8CTST200-32LQXI
• Description: IC MCU 32K FLASH 32UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-32LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2957

SLP_CFG2
21.4.25 SLP_CFG2
This register holds the configuration for I2C sleep, deep sleep, and buzz.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 77
Bit
3:2
1
0
284
Individual Register Names and Addresses:
SLP_CFG2 : 1,ECh
Access : POR
Bit Name
1,ECh
in the Sleep and Watchdog chapter.
ALT_Buzz[1:0]
I2C_ON
LSO_OFF
Name
Sleep Configuration Register 2
7
6
Description
These bits control additional selections for POR/LVD buzz rates.
00
01
10
11
This bit enables the standby regulator in I2C sleep mode at a level sufficient to supply the I2C cir-
cuitry.
This bit disables the LSO oscillator when in sleep state.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Compatibility mode, buzz rate is determined by PSSDC bits.
Duty cycle is 1/32768.
Duty cycle is 1/8192.
Reserved.
5
4
3
ALT_Buzz[1:0]
RW : 0
2
1,ECh
I2C_ON
Register Definitions on
RW : 0
1
LSO_OFF
RW : 0
0
[+] Feedback