CY7C63743-PXC Cypress Semiconductor Corp, CY7C63743-PXC Datasheet - Page 20

• Manufacturer Part Number: CY7C63743-PXC
• Description: IC MCU 8K USB/PS2 LS 24DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63743-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 16
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1621

Bit [5:4]: Reserved
Bit [3:0]: Byte Count Bit [3:0]
USB Regulator Output
The VREG pin provides a regulated output for connecting the
pull-up resistor required for USB operation. For USB, a 1.5-kΩ
resistor is connected between the D– pin and the V
to indicate low-speed USB operation. Since the VREG output
has an internal series resistance of approximately 200Ω, the
external pull-up resistor required is R
The regulator output is placed in a high-impedance state at reset,
and must be enabled by firmware by setting the VREG Enable
bit in the USB Status and Control Register (Figure 14). This
simplifies the design of a combination PS/2-USB device, since
the USB pull-up resistor can be left in place during PS/2
operation without loading the PS/2 line. In this mode, the V
pin can be used as an input and its state can be read at port P2.0.
Refer to Figure for the Port 2 data register. This input has a TTL
threshold.
In suspend mode, the regulator is automatically disabled. If
VREG Enable bit is set (Figure 14), the VREG pin is pulled up to
V
state in suspend mode
Note that enabling the device for USB (by setting the Device
Address Enable bit,
Document #: 38-08022 Rev. *D
CC
Byte Count Bits indicate the number of data bytes in a trans-
action: For IN transactions, firmware loads the count with the
number of bytes to be transmitted to the host from the end-
point FIFO. Valid values are 0 to 8 inclusive. For OUT or SET-
UP transactions, the count is updated by hardware to the
number of data bytes received, plus 2 for the CRC bytes. Valid
values are 2 to 10 inclusive.
For Endpoint 0 Count Register, whenever the count updates
from a SETUP or OUT transaction, the count register locks
and cannot be written by the CPU. Reading the register un-
locks it. This prevents firmware from overwriting a status up-
date on incoming SETUP or OUT transactions before firm-
ware has a chance to read the data.
with an internal 6.2-kΩ resistor. This holds the proper V
Figure
15) activates the internal regulator,
PU
(see Section ).
REG
voltage,
REG
OH
even if the VREG Enable bit is cleared to 0. This insures proper
USB signaling in the case where the VREG pin is used as an
input, and an external regulator is provided for the USB pull-up
resistor. This also limits the swing on the D– and D+ pins to about
1V above the internal regulator voltage, so the Device Address
Enable bit normally should only be set for USB operating modes.
The regulator output is only designed to provide current for the
USB pull-up resistor. In addition, the output voltage at the VREG
pin is effectively disconnected when the CY7C637xxC device
transmits USB from the internal SIE. This means that the VREG
pin does not provide a stable voltage during transmits, although
this does not affect USB signaling.
PS/2 Operation
The CY7C637xxC parts are optimized for combination USB or
PS/2 devices, through the following features:
The PS/2 on-chip support circuitry is illustrated in
1. USB D+ and D– lines can also be used for PS/2 SCLK and
2. An interrupt is provided to indicate a long LOW state on the
3. Internal PS/2 pull-up resistors can be enabled on the SCLK
4. The controlled slew rate outputs from these pins apply to both
5. The state of the SCLK and SDATA pins can be read, and can
6. The V
SDATA pins, respectively. With USB disabled, these lines can
be placed in a high-impedance state that will pull up to V
(Disable USB by clearing the Address Enable bit of the USB
Device Address Register, Figure 15).
SDATA pin. This eliminates the need to poll this pin to check
for PS/2 activity. Refer to Section for more details.
and SDATA lines, so no GPIO pins are required for this task
(bit 7, USB Status and Control Register, Figure 14).
USB and PS/2 modes to minimize EMI.
be individually driven LOW in an open drain mode. The pins
are read at bits [5:4] of Port 2, and are driven with the Control
Bits [2:0] of the USB Status and Control Register.
that a USB pull-up resistor on the D–/SDATA pin will not
interfere with PS/2 operation (bit 6, USB Status and Control
Register).
REG
pin can be placed into a high-impedance state, so
CY7C63722C
CY7C63723C
CY7C63743C
Page 20 of 53
Figure
19.
CC
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