CY7C64714-56PVXC Cypress Semiconductor Corp, CY7C64714-56PVXC Datasheet - Page 17

• Manufacturer Part Number: CY7C64714-56PVXC
• Description: IC MCU USB EZ FX1 16KB 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64714-56PVXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5-1. FX1 Pin Definitions (continued)
Document #: 38-08039 Rev. *C
TQFP
Port B
PORT C
128
92
44
45
46
47
54
55
56
57
72
73
74
75
76
TQFP
100
74
34
35
36
37
44
45
46
47
57
58
59
60
61
QFN
56
40
18
19
20
21
22
23
24
25
PA7 or
FLAGD or
SLCS#
PB0 or
FD[0]
PB1 or
FD[1]
PB2 or
FD[2]
PB3 or
FD[3]
PB4 or
FD[4]
PB5 or
FD[5]
PB6 or
FD[6]
PB7 or
FD[7]
PC0 or
GPIFADR0
PC1 or
GPIFADR1
PC2 or
GPIFADR2
PC3 or
GPIFADR3
PC4 or
GPIFADR4
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Default
[8]
(PC0)
(PC1)
(PC2)
(PC3)
(PC4)
(PA7)
(PB0)
(PB1)
(PB2)
(PB3)
(PB4)
(PB5)
(PB6)
(PB7)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by PORTCCFG.0
PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.1
PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.2
PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.3
PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.4
PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
Description
CY7C64713/14
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