MPC852TVR50A Freescale Semiconductor, MPC852TVR50A Datasheet - Page 6

IC MPU POWERQUICC 50MHZ 256PBGA

MPC852TVR50A

Manufacturer Part Number
MPC852TVR50A
Description
IC MPU POWERQUICC 50MHZ 256PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC Ir
Datasheet

Specifications of MPC852TVR50A

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
1.8V
Mounting Type
Surface Mount
Package / Case
256-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Development Tools By Supplier
MPC852TADS-KIT
Maximum Clock Frequency
50 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
8 KB
I/o Voltage
3.3 V
Interface Type
SPI, UART
Minimum Operating Temperature
0 C
Program Memory Size
4 KB
Program Memory Type
EPROM/Flash
Core Size
32 Bit
Cpu Speed
50MHz
Embedded Interface Type
SPI
Digital Ic Case Style
BGA
No. Of Pins
256
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Maximum Tolerated Ratings
3
This section provides the maximum tolerated voltage and temperature ranges for the MPC852T.
provides the maximum ratings and operating temperatures.
1
2
Figure 2
6
Supply voltage
Input voltage
Storage temperature range
The power supply of the device must start its ramp from 0.0 V.
Functional operating conditions are provided with the DC electrical specifications in
stress ratings only; functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than V
normal operation (that is, if the MPC852T is unpowered, a voltage greater than 2.5 V must not be applied to its inputs).
Maximum Tolerated Ratings
shows the undershoot and overshoot voltages at the interface of the MPC852T.
2
1
Rating
V
Note:
V
1. t
IH
IL
interface
V
Figure 2. Undershoot/Overshoot Voltage for V
V
DDH
DDH
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
/V
GND – 0.3 V
GND – 0.7 V
refers to the clock period associated with the bus clock interface.
/V
V
DDL
DDH
DDL
+ 20%
/V
+ 5%
GND
Table 1. Maximum Tolerated Ratings
DDL
V
V
V
Difference between V
V
T
stg
DDL
DDH
DDSYN
in
(core voltage)
(I/O voltage)
Symbol
Not to Exceed 10%
of t
DDL
interface
to V
1
DDSYN
DDH
DDH
. This restriction applies to power-up and
Table
and V
5. Absolute maximum ratings are
GND – 0.3 to V
DDL
– 55 to +150
– 0.3 to 3.4
– 0.3 to 3.4
– 0.3 to 4
Value
100
Freescale Semiconductor
DDH
Table 1
Unit
mV
°C
V
V
V
V

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