MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 79
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MPC8308VMAGD
Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8308VMAGD.pdf
(90 pages)
2.MPC8308VMAGD.pdf
(2 pages)
3.MPC8308VMAGD.pdf
(1170 pages)
4.MPC8308VMAGD.pdf
(14 pages)
Specifications of MPC8308VMAGD
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8308VMAGD
Manufacturer:
FREESCAL
Quantity:
300
Company:
Part Number:
MPC8308VMAGD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8308VMAGD
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MPC8308VMAGD400/266
Manufacturer:
FREESCAL
Quantity:
300
Company:
Part Number:
MPC8308VMAGDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
coherent system bus clock (csb_clk).
for select csb_clk to SYS_CLK_IN ratios.
21.3
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
not listed in
Freescale Semiconductor
0–1
nn
11
00
01
10
00
01
10
00
01
10
00
01
RCWL[COREPLL]
Core PLL Configuration
Table 58
0010
0100
0101
nnnn
0000
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
Core VCO frequency = core frequency × VCO divider. The VCO divider,
which is determined by RCWLR[COREPLL], must be set properly so that
the core VCO frequency is in the range of 400–800 MHz.
2–5
csb_clk :Input Clock Ratio
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2
should be considered as reserved.
Table 58
6
0
n
0
0
0
1
1
1
0
0
0
1
1
SPMF
(PLL off, csb_clk clocks core directly)
shows the encodings for RCWL[COREPLL]. COREPLL values that are
2:1
4:1
5:1
Table 58. e300 Core PLL Configuration
core_clk: csb_clk Ratio
Table 57. CSB Frequency Options
Table 57
PLL bypassed
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
n/a
1:1
1:1
1:1
2:1
2:1
2:1
shows the expected frequency values for the CSB frequency
NOTE
125
1
25
Input Clock Frequency (MHz)
(PLL off, csb_clk clocks core directly)
33.33
VCO Divider (VCOD)
133
167
PLL bypassed
n/a
2
4
8
2
4
8
2
4
8
2
4
66.67
133
2
Clocking
79