MC68030RC25C Freescale Semiconductor, MC68030RC25C Datasheet - Page 187

• Manufacturer Part Number: MC68030RC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Im
7-26
7.2.7
the on-chip caches, the bus may operate differently when caching is enabled.
The slave device must supply as much aligned data on the data bus as its
the lower word boundary on D16-D31 of the data bus. For a byte port, the
the read cycle. If the bus cycle terminates abnormally, the MC68030 does not
The caches can also affect the assertion of AS and the operation of a read
the OCS signal, if appropriate). If an internal cache hit occurs, the external
time specified from the negation of ECS to the next assertion of ECS (refer
cycle due to an instruction cache hit, the bus controller asserts ECS on the
cycle. Therefore, since instruction and data accesses are mixed, it is possible
to see multiple successive ECS assertions on the external bus if the processor
The organization and requirements of the on-chip instruction and data caches
affect the interpretation of the DSACKx and STERM signals. Since the MC68030
attempts to load all data operands and instructions that are cachable into
Specifically, on cachable read cycles that terminate normally, the low-order
address signals (A0 and A1) and the size signals do not apply.
port size allows, regardless of the requested operand size. This means that
an 8-bit port must supply a byte, a 16-bit port must supply a word, and a
32-bit port must supply an entire long word. This data is loaded into the
cache. For a 32-bit port, the slave device ignores A0 and A1 and supplies the
device supplies the addressed byte on D24-D31.
not be cached, the device must assert cache inhibit in (CIIN) as it terminates
cache the data. For details of interactions of port sizes, misalignments, and
cache filling, refer to 6.1.3 Cache Filling.
cycle. The search of the appropriate cache by the processor begins when the
controller may also initiate an external bus cycle in case the requested item
another read or write cycle, the bus controller asserts the EC,~ signal (and
cycle aborts, and AS is not asserted. This makes it possible to have ECS
asserted on multiple consecutive clock cycles. Notice that there is a minimum
to MC68030EC/D, MC68030 E/ectrica/ Specifications.
Instruction prefetches can occur every other clock so that if, after an aborted
next clock, this second cycle is for a data fetch. However, data accesses that
hit in the data cache can also cause the assertion of ECS and an aborted
long word beginning at the long-word boundary on the data bus. For a
16-bit port, the device ignores A0 and supplies the entire word beginning at
If the addressed device cannot supply port-sized data or if the data should
microsequencer requires an instruction or a data item. At this time, the bus
is not resident in the instruction or data cache. If the bus is not occupied with
C a c h e
Interactions
MC68030 USER'S MANUAL
MOTOROLA