MC68030RC25C Freescale Semiconductor, MC68030RC25C Datasheet - Page 45

• Manufacturer Part Number: MC68030RC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

1-16
1.8 PIPELINED ARCHITECTURE
1.9 THE CACHE MEMORIES
two on-chip logical caches, a data cache, and an instruction cache.
four long words consecutively. The burst mode of operation not only fills
the cache efficiently but also captures adjacent instruction or data items that
the executing task.
words of a single instruction or three consecutive instructions to be decoded
each containing a block of four long words (16 bytes). The processor fills the
cache entries either one long word at a time or, during burst mode accesses,
the data item to be stored in the cache, depending on the write allocation
frames. Memory management assigns a physical base address to a logical
and memory one or more pages at a time.
The MC68030 uses a three-stage pipelined internal architecture to provide
for optimum instruction throughput. The pipeline allows as many as three
concurrently.
Due to locality of reference, instructions and data that are used in a program
have a high probability of being reused within a short time. Additionally,
instructions and data operands that reside in proximity to the instructions
and data currently in use also have a high probability of being utilized within
a short period. To exploit these locality characteristics, the MC68030 contains
Each of the caches stores 256 bytes of information,
are likely to be required in the near future due to locality characteristics of
The caches improve the overall performance of the system by reducing the
of cache techniques to all memory accesses. During a write cycle, the data
cache circuitry writes data to a cached data item as well as to the item in
into fixed-size pages that contain the same number of bytes as the page
page. The system software then transfers data between secondary storage
number of bus cycles required by the processor to fetch information from
memory and by increasing the bus bandwidth available for other bus masters
in the system. Addition of the data cache in the MC68030 extends the benefits
memory, maintaining consistency between data in the cache and that in
memory. However, writing data that is not in the cache may or may not cause
policy selected in the cache control register (CACR).
MC68030 USER'S MANUAL
organized
as 16 entries,
MOTOROLA