MC68030RC25C Freescale Semiconductor, MC68030RC25C Datasheet - Page 539

• Manufacturer Part Number: MC68030RC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

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12.4.1 Access Time Calculations
12-14
the negating strobes and to avoid any bus contention with the following bus
ways accessed in fewer than "no wait states", regardless of the external
The timing paths that are typically critical in any memory interface are illus-
trated and defined in Figure 12-8. For burst transfers, the first long word
transferred also uses these parameters, but the subsequent transfers are
The type of device that is interfaced to the MC68030 determines exactly which
for dynamic devices since the cycle must be validated before an access can
Write operations also use this data bus timing to allow data hold times from
cycle. This usually allows the system to be designed with a minimum of bus
buffers and latches.
One of the benefits of the MC68030's on-chip caches is that the effect of
external wait states on performance is lessened because the caches are al-
unique among other general-purpose microprocessors.
different and are discussed in 12.4.2 Burst Mode Cycles.
of the paths is most critical. The address-to-data paths are typically the critical
paths for static devices since there is no penalty for initiating a cycle to these
devices and later validating that access with the appropriate bus control
signal. Conversely, the address-strobe-to-data-valid path is often most critical
be initiated. For devices that signal termination of a bus cycle before data is
validated (e.g., error detection and correction hardware and some external
caches) to improve performance, the critical path may be from the address
or strobes to the assertion of BERR (or BERR and HALT). Finally, the address-
valid-to-DSACKx-or-STERM-asserted path is most critical for very fast devices
and external caches, since the time available between when the address is
valid and when DSACKx or STERM must be asserted to terminate the bus
cycle is minimal. Table 12-2 provides the equations required to calculate the
various memory access times assuming a 50-percent duty cycle clock.
During read operations, M68000 processors latch data on the last falling clock
edge of the bus cycle, one-half clock before the bus cycle ends (burst mode
is a special case). Latching data here, instead of the next rising clock edge,
helps to avoid data bus contention with the next bus cycle and allows the
MC68030 to receive the data into its execution unit sooner for a net perform-
ance increase.
memory configuration. This feature makes the MC68030 (and MC68020)
MC68030 USER'S MANUAL
MOTOROLA