MC68030RC25C Freescale Semiconductor, MC68030RC25C Datasheet - Page 464

• Manufacturer Part Number: MC68030RC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

SECTION 11
MOTOROLA
11.1
The MC68030 can overlap data writes with instruction cache reads, data cache
time for an instruction or operation is highly dependent on memory speeds
tasking or real-time systems can predict task switch overhead, maximum
P E R F O R M A N C E
to over 100 clocks. Factors affecting the execution time are the preceding
To increase the average performance of the MC68030, certain tradeoffs were
This section describes the instruction execution and operations (table
searches, etc.) of the MC68030 in terms of external clock cycles. It provides
accurate execution and operation timing guidelines but not exact timings for
every possible circumstance. This approach is used since exact execution
and other variables. The timing numbers presented in this section allow the
assembly language programmer or compiler writer to predict actual cache-
case and average no-cache-case timings needed to evaluate the performance
of the MC68030. Additionally, the timings for exception processing, context
switching, and interrupt processing are included so that designers of multi-
interrupt latency, and similar timing parameters.
eliminate clock frequency dependencies.
The MC68030 maximizes average performance at the expense of worst case
performance. The time spent executing one instruction can vary from zero
and following instructions, the instruction stream alignment, residency of
operands and instruction words in the caches, residency of address trans-
worst case behavior. For ex&mple, burst filling increases performance by
and a cache for a longer period.
cache reads can be overlapped with instruction cache fills and/or micro-
INSTRUCTION EXECUTION TIMING
In this section, instruction and operation times are shown in clock cycles to
lations in the address translation cache, and operand alignment.
made to increase best case performance and to decrease the occurrence of
prefetching data for later accesses, but it commits the external bus controller
reads, and/or microsequencer execution. Instruction cache reads can be over-
lapped with data cache fills and/or microsequencer activity. Similarly, data
T R A D E O F F S
MC68030 USER'S MANUAL
11-1
11