MC68030RC25C Freescale Semiconductor, MC68030RC25C Datasheet - Page 465

• Manufacturer Part Number: MC68030RC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

11
11-2
11.2 RESOURCE SCHEDULING
11.2.1 Microsequencer
11.2.2 Instruction Pipe
directly related to instruction boundaries, it is impossible to make accurate
estimates of the time required to execute a particular instruction without
knowing the complete context within which the instruction is executing. The
The microsequencer is either executing microinstructions or awaiting com-
pletion of accesses that are necessary to continue executing microcode. The
bus controller is responsible for all bus activity. The microsequencer controls
the bus controller, instruction execution, and internal processor operations
such as calculation of effective addresses and setting of condition codes. The
microsequencer initiates instruction word prefetches and controls the vali-
dation of instruction words in the instruction pipe.
The MC68030 contains a three-word instruction pipe where instruction op-
codes are decoded. As shown in Figure 11-1, instruction words (instruction
operation words and all extension words) enter the pipe at stage B and
it reaches stage D of the pipe. Each of the pipe stages has a status bit that
that was terminated abnormally. Stages of the pipe are only filled in response
to specific prefetch requests issued by the microsequencer.
Words are loaded into the instruction pipe from the cache holding register.
While the individual stages of the pipe are only 16 bits wide, the cache holding
obtained from the instruction cache or the external bus in response to a
prefetch request from the microsequencer. When the microsequencer re-
sequencer activity. The execution of an instruction that only accesses on-
chip registers can be overlapped entirely with a concurrent data write gen-
erated by a previous instruction, if prefetches generated by that instruction
are resident in the instruction cache.
Some of the variability in instruction execution timings results from the over-
lap of resource utilization. The processor can be viewed as consisting of eight
independently scheduled resources. Since very little of the scheduling is
position of these resources within the MC68030 is shown in Figure 11-1.
proceed to stages C and D. An instruction word is completely decoded when
reflects whether the word in the stage was loaded with data from a bus cycle
register is 32 bits wide and contains the entire long word. This long word is
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