MC68030RC25C Freescale Semiconductor, MC68030RC25C Datasheet - Page 295

• Manufacturer Part Number: MC68030RC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8-28
8.2.1 Special Status Word (SSW)
I Fc I FB J RC I RB I×
StZE
"1 =Rerun Faulted bus Cycle, or run pending
RC
RB
DF
RM
RW
FC2-FCO --Address space for data cycle
to the instruction stream, data stream, or both. The high-order half of the
values in the pipe after an address error or a bus error, if necessary. If a rerun
stage of the pipe (if it is required). If the rerun and fault bits are set for a
for that stage. The address space for the bus cycle is the program space for
the privilege level indicated in the copy of the status register on the stack. If
a rerun bit is cleared, the words on the stack for the corresponding stages
The internal SSW (see Figure 8-9) is one of several registers saved as part
and the long bus cycle fault f o r m a t include this word at offset $A. The bus
cycle fault stack frame formats are described in detail at the end of this
section.
FC
FB
X = For internal use only
The SSW information indicates w h e t h e r the fault was caused by an access
SSW contains t w o status bits each for the B and C stages of the instruction
pipe. The fault bits (FB and FC) indicate that the processor attempted to use
a stage (B or C) and found it to be marked invalid due to a bus error on the
prefetch for that stage. The fault bits can be used by a bus error handler to
determine the cause(s) of a bus error exception. The rerun flag bits (RB and
RC) are set to indicate that a fault occurred during a prefetch for the corre-
sponding stage. A rerun bit is always set when the corresponding fault bit
is set. The rerun bits indicate that the word in a stage of the instruction pipe
is invalid, and the state of the bits can be used by a handler to repair the
bit is set when the processor executes an RTE instruction, the processor m a y
execute a bus cycle to prefetch the instruction word for the corresponding
stage of the pipe, the RTE instruction automatically reruns the prefetch cycle
of the bus fault exception stack frame. Both the short bus cycle fault f o r m a t
0 = Do not rerun bus sycle
15
14
--Read-m0dify-write on data cycle
-- Size code for data cycle
-- Fault on stage C of the instruction pipe
--Fault on stage B of the instruction pipe
--Rerun flag for stage C of the instruction pipe*
--Rerun flag for stage B of the instruction pipe*
--Fault/rerun flag for date
-- Read/write for data cycle -- 1 = read, 0 = write
13
12
Figure 8-9. Special Status Word (SSW)
11
MC68030 USER'S MANUAL
I× I× I0F IBM I RWI S,ZE I Xl
cycle*
10
<
prefetch
9
8
7
6
5
4
3
2 ~'~j
I
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MOTOROLA
FC2 00
:
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