PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 21

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Notes:
5345D–HIREL–07/06
Symbol
t
t
KHKL
SYSCLK
/
(4)
1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) fre-
2. Assumes lightly-loaded, single-processor system.
3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V.
4. Timing is guaranteed by design and characterization.
5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.
6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at -3 dB.
7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for
quency, CPU (core) frequency and PLL (VCO) frequency don’t exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in
PLL_CFG[0:4] settings
PLL lock after a stable V
when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Characteristic
SYSCLK duty cycle measured at OV
SYSCLK jitter
Internal PLL relock time
Figure 7-1
Figure 7-1.
VM = Midpoint Voltage (OV
(5)(6)
SYSCLK
DD
(7)
and SYSCLK are reached during the power-on reset sequence. This specification also applies
provides the SYSCLK input timing diagram.
SYSCLK Input Timing Diagram
DD
VM
/2
t KHKL
DD
Min
40
t SYSCLK
/2)
V
–
–
867 MHz
DD
= 1.3V
VM
±150
Max
100
60
“Core Clocks and PLL Configuration” on page 47
Maximum Processor Core Frequency
Min
V
40
1000 MHz
–
–
DD
VM
= 1.3V
C V IL
±150
Max
100
60
Min
V
40
C V IH
1200 MHz
–
–
DD
t KR
= 1.3V
±150
Max
100
60
Min
V
40
1267 MHz
–
–
DD
= 1.3V
PC7457
±150
Max
100
60
for valid
t KF
Unit
ps
µs
%
21