PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 5

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

5345D–HIREL–07/06
– Four integer units (IUs) that share 32 GPRs for integer operands
– Five-stage FPU and a 32-entry FPR file
– Four vector units and 32-entry vector register file (VRs)
– Three-stage load/store unit (LSU)
Eight-entry link register stack to predict the target address of Branch Conditional to
Link Register (BCLR) instructions
Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions
IU2 executes miscellaneous instructions including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions
Fully IEEE 754-1985-compliant FPU for both single- and double-precision
operations
Supports non-IEEE mode for time-critical operations
Hardware support for denormalized numbers
Thirty-two 64-bit FPRs for single- or double-precision operands
Vector permute unit (VPU)
Vector integer unit 1 (VIU1) handles short-latency AltiVec integer instructions, such
as vector add instructions (vaddsbs, vaddshs, and vaddsws, for example)
Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such
as vector multiply add instructions (vmhaddshs, vmhraddshs, and vmladduhm, for
example)
Vector floating-point unit (VFPU)
Supports integer, floating-point, and vector instruction load/store traffic
Four-entry vector touch queue (VTQ) supports all four architected AltiVec data
stream operations
Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-
cycle throughput
Four-cycle FPR load latency (single, double) with one-cycle throughput
No additional delay for misaligned access within double-word boundary
PC7457
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