PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 49

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

15.1.2
Table 15-2.
Notes:
5345D–HIREL–07/06
Frequency
1050
1100
1150
1200
1250
1300
(MHz)
Core
1000
500
533
550
600
650
666
700
733
800
866
933
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the
4. In PLL-off mode, no clocking occurs inside the PC7455 regardless of the SYSCLK input.
1. The core and L3 frequencies are for reference only. Note that maximum L3 frequency is design dependent. Some examples
2. Not all core frequencies are supported by all speed grades; see
(2)
(2)
(2)
(2)
(2)
(2)
L3 Clocks
bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at one-half the
frequency of SYSCLK and offset in phase to meet the required input setup t
22). The result is that the processor bus frequency is one-half SYSCLK while the internal processor is clocked at SYSCLK
frequency. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
may represent core or L3 frequencies which are not useful, not supported, or not tested for the PC7457; see
Specifications” on page 24
quency specifications.
Sample Core-to-L3 Frequencies
250
266
275
300
325
333
350
367
400
433
467
500
525
550
575
600
638
650
÷2
÷2.5
200
213
220
240
260
266
280
293
320
347
373
400
420
440
460
480
500
520
The PC7457 generates the clock for the external L3 synchronous data SRAMs by dividing the
core clock frequency of the PC7457. The core-to-L3 frequency divisor for the L3 PLL is selected
through the L3_CLK bits of the L3CR register. Generally, the divisor must be chosen according
to the frequency supported by the external RAMs, the frequency of the PC7457 core, and timing
analysis of the circuit board routing.
that can be obtained for a given set of core frequencies.
167
178
183
200
217
222
233
244
266
289
311
333
350
367
383
400
417
433
÷3
for valid L3_CLK frequencies and for more information regarding the maximum L3 frequency.
÷3.5
143
152
157
171
186
190
200
209
230
248
266
285
300
314
329
343
357
371
(1)
125
133
138
150
163
167
175
183
200
217
233
250
263
275
288
300
313
325
÷4
÷4.5
111
118
122
133
144
148
156
163
178
192
207
222
233
244
256
267
278
289
Table 15-2
100
107
110
120
130
133
140
147
160
173
187
200
191
200
209
218
227
236
÷5
Table 7-2 on page 20
÷5.5
100
109
118
121
127
133
145
157
170
182
191
200
209
218
227
236
91
97
shows various example L3 clock frequencies
IVKH
and hold time t
100
108
111
117
122
133
145
156
166
175
183
192
200
208
217
÷6
83
89
92
for minimum and maximum core fre-
÷6.5
100
102
108
113
123
133
144
154
162
169
177
185
192
200
77
82
85
92
IXKH
(see
100
105
114
124
133
143
150
157
164
171
179
186
÷7
71
76
79
86
93
95
Table 7-3 on page
PC7457
÷7.5
107
115
124
133
140
147
153
160
167
173
67
71
73
80
87
89
93
98
“L3 Clock AC
100
108
117
125
131
138
144
150
156
163
÷8
63
67
69
75
81
83
88
92
49