PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 29

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 7-7.
Notes:
5345D–HIREL–07/06
Symbol
t
t
t
t
t
t
t
t
t
L3CR
L3DVEH
L3DXEH
L3CHDV
L3CHOV
L3CHDX
L3CHOX
L3CLDZ
L3CHOZ
, t
L3CF
, t
, t
, t
, t
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of G
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the ris-
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in
4. t
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in
7. t
L3CLDV
L3DVEL
L3DXEL
L3CLDX
ing or falling edge of the input L3_ECHO_CLKn (see
input setup time specifications, this will be treated as negative input setup time.
valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising)
edges of L3_ECHO_CLKn at any frequency.
L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a
purely resistive 50 load (see
other output valid time specifications, this will be treated as negative output valid time.
by an internal clock delayed in phase by 90 . Therefore, there is a frequency component to the output valid and output hold
times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock
prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
L3_CLK
L3_CLK
L3 Bus Interface AC Timing Specifications for MSUG2 at Recommended Operating Conditions
(see
/4 is one-fourth the period of L3_CLKn. This parameter indicates that the PC7457 can latch an input signal that is
/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched
Parameter
L3_CLK rise and fall time
Setup times: Data and parity
Input hold times: Data and parity
Valid times: Data and parity
Valid times: All other outputs
Output hold times: Data and parity
Output hold times: All other outputs
L3_CLK to high impedance: Data and parity
L3_CLK to high impedance: All other outputs
page
12)
An internal circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within
the valid data window at the internal receiving latches. This delayed clock is used to capture the
data into these latches which comprise the receive FIFO. This clock is asynchronous to all other
processor clocks. This latched data is subsequently read out of the FIFO synchronously to the
processor clock. The time between writing and reading the data is set by the using the sample
point settings defined in the L3CR
specifications for the configuration as shown in Figure 9, assuming the timing relationships
shown in
Figure 7-7
Figure 7-5 on page
(1)
(5)(6)(7)(8)
(5)(7)(8)
(2)(3)(4)
and the loading shown in
(2)(4)
(5)(6)(7)(8)
(5)(7)(8)
26).
Figure 7-7 on page
register.Table 7-7
(-t
(t
(t
(t
+ 0.90
+ 0.85
L3CLK
L3CLK
L3CLK
- 0.60
- 0.50
L3CLK
Min
–
–
–
–
–
/4)
/4)
/4)
/4)
Figure 7-5 on page
(-t
(-t
30). Input timings are measured at the pins.
(t
(t
+ 0.60
+ 0.65
+ 0.60
+ 0.65
L3CLK
L3CLK
All Speed Grades
L3CLK
L3CLK
0.75
Min
–
–
–
–
Figure 7-7 on page
provides the L3 bus interface AC timing
V
/4)
/4)
/4)
/4)
DD
.
Figure
(-t
(t
(t
(t
+ 0.70
+ 0.70
L3CLK
L3CLK
L3CLK
- 0.50
- 0.50
L3CLK
26.
Max
–
–
–
–
–
7-7. For consistency with other
(9)
/4)
/4)
/4)
/4)
30. For consistency with
(-t
(-t
(t
(t
+ 0.50
+ 0.65
+ 0.60
+ 0.65
L3CLK
L3CLK
L3CLK
L3CLK
Max
0.75
–
–
–
–
PC7457
/4)
/4)
/4)
/4)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
29