PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 31

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Notes:
7.2.5
Table 7-8.
Notes:
5345D–HIREL–07/06
Symbol
t
t
t
t
t
t
t
t
t
L3CR
L3DVEH
L3DXEH
L3CHDV
L3CHOV
L3CHDX
L3CHOX
L3CHDZ
L3CHOZ
, t
L3CF
1. t
2. VM = Midpoint Voltage (GV
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV
2. Timing behavior and characterization are currently being evaluated.
3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal
5. Assumes default value of L3OHCR. See
L3_ECHO_CLK[0,1,2,3]
L3 Bus AC Specifications for PB2 and Late Write SRAMs
the input L3_ECHO_CLKn (see
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see
7-7).
information.
Inputs
L3DVEH
L3 Data and Data
L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs at Recommended Operating
Conditions (see
Parameter
L3_CLK rise and fall time
Setup times: Data and parity
Input hold times: Data and parity
Valid times: Data and parity
Valid times: All other outputs
Output hold times: Data and parity
Output hold times: All other outputs
L3_CLK to high impedance: Data and parity
L3_CLK to high impedance: All other outputs
and t
Parity Inputs
L3DVEL
When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as
shown in
signal is output to each SRAM to latch address, control, and write data. Read data is launched
by the SRAM synchronous to the delayed L3_CLKn signal it received. The PC7457 needs a
copy of that delayed clock which launched the SRAM read data to know when the returning data
will be valid. Therefore, L3_ECHO_CLK1 and L3_ECHO_CLK3 must be routed halfway to the
SRAMs and returned to the PC7457 inputs L3_ECHO_CLK0 and L3_ECHO_CLK2, respec-
tively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are phase-aligned with the input clock
received at the SRAMs. The PC7457 will latch the incoming data on the rising edge of
L3_ECHO_CLK0 and
ifications for the configuration shown in
7-9
as drawn here will be negative numbers, that is, input setup time will be time after the clock edge.
and the loading of
page
DD
Figure 7-8 on page
12)
/2)
(1)(2)
Figure 7-7 on page
(2)(4)(5)
(5)
(2)(3)
(2)(3)
(2)(4)(5)
(2)(5)
“Effects of L3OHCR Settings on L3 Bus AC Specifications” on page
L3_ECHO_CLK2.Table 7-8
Figure 7-5 on page
t L3DVEH
t L3DXEH
VM
(2)
32. These SRAMs are synchronous to the PC7457; one L3_CLKn
(2)
30). Input timings are measured at the pins.
VM
Figure
t L3DVEL
26.
7-8, assuming the timing relationships of
provides the L3 bus interface AC timing spec-
VM
DD
Min
0.1
1.4
1.0
All Speed Grades
–
–
–
–
–
–
.
t L3DXEL
VM
Max
0.75
0.7
2.5
1.8
3.0
3.0
–
–
–
VM
PC7457
27” for more
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
Figure
31