PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 53

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

15.7
5345D–HIREL–07/06
JTAG Configuration Signals
During inactive periods on the bus, the address and transfer attributes may not be driven by any
master and may, therefore, float in the high-impedance state for relatively long periods of time.
Because the PC7457 must continually monitor these signals for snooping, this float condition
may cause excessive power draw by the input receivers on the PC7457 or by other receivers in
the system. It is recommended that these signals be pulled up through weak (4.7 k ) pull-up
resistors by the system, or that they may be otherwise driven by the system during inactive peri-
ods of the bus. The snooped address and transfer attribute inputs are A[0:35], AP[0:4], TT[0:4],
CI, WT, and GBL.
If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through
weak pull-down resistors. If the PC7457 is in 60x bus mode, DTI[0:3] must be pulled low to GND
through weak pull-down resistors.
The data bus input receivers are normally turned off when no read operation is in progress and,
therefore,
ever, may require pull-ups, or that those signals be otherwise driven by the system during
inactive periods by the system. The data bus signals are D[0:63] and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled
through HID0, the input receivers for those pins are disabled, and those pins
resistors and should be left unconnected by the system. If all parity generation is disabled
through HID0, then all parity checking should also be disabled through HID0, and all parity pins
may be left unconnected by the system.
The L3 interface does not normally require pull-up resistors.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is
optional in the IEEE 1149.1 specification, but is provided on all processors that implement the
PowerPC architecture. While it is possible to force the TAP controller to the reset state using
only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the
TRST signal is asserted during power-on reset. Because the JTAG interface is also used for
accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not
practical.
The COP function of these processors allows a remote computer system (typically, a PC with
dedicated hardware and debugging software) to access and control the internal operations of
the processor. The COP interface connects primarily through the JTAG port of the processor,
with some additional status monitoring signals. The COP port requires the ability to indepen-
dently assert HRESET or TRST in order to fully control the processor. If the target system has
independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, then the COP reset signals must be merged into these signals with logic.
The arrangement shown in
TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP
header will not be used, TRST should be tied to HRESET through a 0 isolation resistor so that
it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan
chain is initialized during power-on. While Freescale recommends that the COP header be
designed into the system as shown in
resistor will allow future access to TRST in the case where a JTAG interface may need to be
wired onto the system in debug situations.
don’t
require pull-up resistors on the bus. Other data bus receivers in the system, how-
Figure 15-1
Figure 15-1 on page
allows the COP port to independently assert HRESET or
50, if this is not possible, the isolation
don’t
PC7457
require pull-up
53