DP8344BV National Semiconductor, DP8344BV Datasheet - Page 138

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

6 0 Reference Section
ANDA And with Accumulator
Syntax
ANDA Rs Rd
ANDA Rs mIr
Affected Flags
N Z
Description
Logically ANDs the source register Rs to the active accumu-
lator and places the result into the destination specified
The destination may be either a register Rd or data memo-
ry via an index register mode mIr Note that register bank
selection determines which accumulator is active
Example
This example demonstrates a way to quickly unload all 11
bits of the three words in the Receiver FIFO when the FIFO
is full The example assumes that the index register IZ
points to the location in data memory where the information
should be stored
Instruction Format
ANDA Rs Rd
T-states
ANDA Rs Rd
ANDA Rs mIr
Bus Timing
ANDA Rs Rd
ANDA Rs mIr
Operation
ANDA Rs Rd
Rs AND accumulator
ANDA Rs mIr
Rs AND accumulator
ANDA Rs mIr
1
15
EXX
MOVE 00000111B A
Pop the first word from the receiver FIFO
ANDA TSR IZ
MOVE RTR IZ
Pop the second word from the receiver FIFO
ANDA TSR IZ
MOVE RTR IZ
Pop the third word from the receiver FIFO
ANDA TSR IZ
MOVE RTR IZ
1
Opcode
1
1 1
1
0
0
a
a
a
a
a
a
9
Figure 6-1
Figure 6-7
register register
register indexed
2
3
Rd
data memory
select alternate banks
place the TSR mask
read bits 8 9
pop bits 0–7
into the accumulator
Rd
(Continued)
4
10
Rs
TL F 9336–7
0
138
Figure 6-1
BIT Bit Test
Syntax
BIT rs n
Affected Flags
N Z
Description
Performs a bit level test by logically ANDing the source reg-
ister rs to the immediate value n The affected flags are
updated but the result is not saved Note that only the ac-
tive registers R0– R15 may be specified for rs The value n
is 8 bits wide
Example
Poll the Transmitter FIFO Empty flag TFE in the Network
Command Flag register NCF
mitter to send the current FIFO data
Poll
Instruction Format
T-states
2
Bus Timing
Operation
rs AND n
0
15
Opcode
1
1
EXX 0 1
BIT
JZ
1
NCF 10000000B
Poll
11
limited register immediate
n
R1 waiting for the Trans-
select main A alt B
All data sent yet
No poll TFE
Yes send next byte(s)
3
rs
0