DP8344BV National Semiconductor, DP8344BV Datasheet - Page 173

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

Timing
Control
Remote
Interface
Interrupt
Control
6 0 Reference Section
6 2 3 Bit Definition Tables
The following tables describe the location and function of all control and status bits in the various BCP addressable special
function registers The Remote Interface Configuration register
included
6 2 3 1 Processor
register
These bits represent the only visibility and control that the processor has into the operation of the remote interface controller The Remote Interface Configuration
RIC
CCS
DW2– 0 Data memory
IW1 0
COD
4TR
LOR
RR
RW
BIC
BIRQ
GIE
IM4–0
Bit
accessible only by a remote processor provides further control functions See Remote Interface section for more information
CPU Clock Select
Wait-state select
Instruction memory DCR 4 3
Wait-state select
Clock Out Disable
4 T-state Read
Lock Out Remote
Remote Read
Remote Write
Bi-directional
Interrupt Control
Bi-directional
Interrupt ReQuest
Global Interrupt
Enable
Interrupt Mask
select
Name
(Continued)
DCR 7
DCR 2– 0
ACR 2
ACR 3
ACR 1
CCR 6
CCR 5
ACR 4
CCR 4
ACR 0
ICR 4 –0
Location
Reset State
11111
111
11
1
0
0
0
0
0
0
X
0
173
RIC
Selects CPU clock frequency
Where OCLK is the frequency of the on-chip oscillator or
the externally applied clock on input X1
Selects from 0 to 7 wait states for accessing data memory
Selects from 0 to 3 wait states for accessing instruction
memory
When high CLK-OUT is at TRI-STATE
When high data memory reads take four T-states
When high a remote processor is prevented from accessing
the BCP or its memory
Set on the trailing edge of a REM-RD pulse if RAE is
asserted and RIC is pointing to Data Memory Cleared by
writing a 1 to RR
Set on the trailing edge of a REM-WR pulse if RAE is
asserted and RIC is pointing to Data Memory Cleared by
writing a 1 to RW
Controls the direction of BIRQ
Updated at the beginning of each instruction cycle
When low disables all maskable interrupts When high
works with IM4– 0 to enable maskable interrupts
Each bit when set high masks an interrupt
IM3 functions as an interrupt mask only when BIRQ is
defined as an input When BIRQ is defined as an output IM3
controls the state of BIRQ
Read Only Reflects the logic level of the BIRQ input
which is addressable only by a remote processor is not
X X X X 1 Receiver
X X X 1 X Transmitter
X X 1 X X Line Turn-Around 3
X 1 X X X Bi-Directional
1 X X X X Timer
0 0 0 0 0 No Mask
IM4– 0
CCS
BIC
0
1
0
1
Interrupt
Function
CPU CLK
OCLK
OCLK 2
Input
Output
BIRQ
1
2
4
5
Priority
High
Low