DP8344BV National Semiconductor, DP8344BV Datasheet - Page 54

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

3 0 Transceiver
ister LJMP conditional and LCALL conditional) will result in
popping the last location of the FIFO presenting a new
word (if present) for future CPU access Data in the FIFO
will propagate from one location to the next in approximate-
ly 10 –15 ns therefore the CPU is easily able to unload the
FIFO with a set of consecutive instructions
If the received bit stream is a multi-byte message the re-
ceiver will continue to process the data and load the FIFO
After the third load (if the CPU has not accessed the FIFO)
the Receive FIFO Full flag RFF will be asserted The prop-
agation delay from the occurrence of the mid-bit edge of the
parity bit of the frame to RFF being set is approximately 5
transceiver clock cycles If there are more than 3 frames in
the incoming message the CPU has approximately one
frame time (sync bit to start of parity bit) to start unloading
the FIFO Failure to do so will result in an overflow error
condition and a resulting loss of data (see Receiver Errors)
If there are no errors detected the receiver will continue to
process the incoming frames until the end of message is
detected The receiver will then return to an inactive state
clearing RA and asserting the Line Turn-Around flag
rors The propagation delay from the occurrence of the
edge starting the first minicode violation to RA cleared and
3270 3299 and 8-bit modes In 5250 modes the assertion
of LTA and clearing of RA are dependent on how the
transmission line ends after the transmission of the three
required fill bits (see 5250 Modes) For the 3270 and 3299
protocols LTA can be used to initiate an immediate trans-
mitter FIFO load for the other protocols an appropriate re-
sponse delay time may be needed LTA is cleared by load-
ing the transmitter’s FIFO writing a one to LTA in the Net-
work Command flag register or by asserting TRES
Receiver Errors
If the Receiver Active flag RA is asserted by the receiver
logic the selected receiver input source is continuously
checked for errors which are reported to the CPU by assert-
ing the Receiver Error flag RE and setting the appropri-
ate receiver error flag in the Error Code Register ECR If a
condition occurs which results in multiple errors being creat-
ed only the first error detected will be latched into ECR
Once an error has been detected and the appropriate error
flag has been set the receiver is disabled clearing RA
and preventing the Line Turn-Around flag and interrupt
LTA indicating that a message was received with no er-
LTA set is approximately 17 transceiver clock cycles in
(Continued)
FIGURE 3-8 Timing of Receiver Flags Relative to Incoming Data
54
mains asserted if signal transitions continue to be detected
on the input
5 error flags are provided in ECR
To determine which error has occurred the CPU must read
Codes control bit SEC and reading RTR The ECR is
only 5 bits wide therefore the upper 3 bits are still the out-
put of the receive FIFO (see Figure 3-6) All instructions with
ter LJMP conditional and LCALL conditional) will clear the
error condition and return the receiver to idle allowing the
receiver to again monitor the incoming data stream for a
new start sequence The SEC control bit must be de-as-
serted to read the FIFO’s data from RTR
If data is present in the FIFO when the error occurs the
Data Available flag DAV is de-asserted when the error is
detected and re-asserted when ECR is read Data pres-
ent in the FIFO before the error occurred is still available to
the CPU The flexibility is provided therefore to read the
error type and still recover data loaded into the FIFO before
the error occurred The Transceiver Reset TRES can be
asserted at any time clearing both Transceiver FIFOs and
the error flags
LTA from being asserted The Line Active flag LA re-
OVF
PAR
IES
LMBT Loss of Mid-Bit Transition Asserted when the
RDIS
ECR
ECR as the source (except BIT CMP JRMK JMP regis-
rsv
7
rsv
This is accomplished by asserting the Select Error
6
Overflow Asserted when the decoder writes to
the first location of the FIFO while RFF is assert-
ed The word in the first location will be over-writ-
ten there will be no effect on the last two loca-
tions
Parity Error Asserted when a received frame
fails an even (word) parity check
Invalid Ending Sequence Asserted during an
expected end sequence when an error occurs in
the mini code-violation Not valid in 5250 modes
expected biphase-encoded mid-bit transition does
not occur within the expected window Indicates a
loss of receiver synchronization
Receiver Disabled While Active Asserted when
an active receiver is disabled by the transmitter be-
ing activated
rsv
5
OVF
4
PAR
3
IES
2
LMBT
1
TL F 9336– 46
RDIS
0