A80386DX33 Intel, A80386DX33 Datasheet - Page 34

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

Intel386
Segments may be overlapped in Real Mode Thus if
a particular segment does not use all 64K bytes an-
other segment can be overlayed on top of the un-
used portion of the previous segment This allows
the programmer to minimize the amount of physical
memory needed for a program
3 3 RESERVED LOCATIONS
There are two fixed areas in memory which are re-
served in Real address mode system initialization
area and the interrupt table area Locations 00000H
through 003FFH are reserved for interrupt vectors
Each one of the 256 possible interrupts has a 4-byte
jump vector reserved for it Locations FFFFFFF0H
through FFFFFFFFH are reserved for system initiali-
zation
3 4 INTERRUPTS
Many of the exceptions shown in Table 2-5 and dis-
cussed in section 2 9 are not applicable to Real
Mode operation in particular exceptions 10 11 14
will not happen in Real Mode Other exceptions
have slightly different meanings in Real Mode Table
3-1 identifies these exceptions
3 5 SHUTDOWN AND HALT
The HLT instruction stops program execution and
prevents the processor from using the local bus until
restarted Either NMI INTR with interrupts enabled
(IF
halt If interrupted the saved CS IP will point to the
next instruction after the HLT
Shutdown will occur when a severe error is detected
that prevents further processing In Real Mode
shutdown can occur under two conditions
34
An interrupt or an exception occur (Exceptions 8
or 13) and the interrupt vector is larger than the
Interrupt table limit too small
CS DS ES FS GS
Segment overrun exception
SS Segment overrun exception
e
1) or RESET will force the Intel386 DX out of
TM
DX MICROPROCESSOR
Function
Interrupt
Number
13
12
8
Table 3-1
INT Vector is not
within table limit
Word memory reference
beyond offset
An attempt to execute
past the end of CS segment
Stack Reference
beyond offset
An NMI input can bring the processor out of shut-
down if the Interrupt Descriptor Table limit is large
enough to contain the NMI interrupt vector (at least
0017H) and the stack has enough room to contain
the vector and flag information (i e SP is greater
than 0005H) Otherwise shutdown can only be exit-
ed via the RESET input
4 PROTECTED MODE
4 1 INTRODUCTION
The complete capabilities of the Intel386 DX are un-
locked when the processor operates in Protected
Virtual Address Mode (Protected Mode) Protected
Mode vastly increases the linear address space to
four gigabytes (2
virtual memory programs of almost unlimited size
(64 terabytes or 2
Mode allows the Intel386 DX to run all of the existing
8086 and 80286 software while providing a sophisti-
cated memory management and a hardware-assist-
ed protection mechanism Protected Mode allows
the use of additional instructions especially opti-
mized for supporting multitasking operating systems
The base architecture of the Intel386 DX remains
the same the registers instructions and addressing
modes described in the previous sections are re-
tained The main difference between Protected
Mode and Real Mode from a programmer’s view is
the increased address space and a different ad-
dressing mechanism
Interrupt Descriptor Table (i e There is not an in-
terrupt handler for the interrupt)
A CALL INT or PUSH instruction attempts to wrap
around the stack segment when SP is not even
(e g pushing a value on the stack when SP
0001 resulting in a stack segment greater than
FFFFH)
ARCHITECTURE
Instructions
Related
e
e
FFFFH
FFFFH
32
46
bytes) and allows the running of
bytes) In addition Protected
Address Location
Instruction
Instruction
Instruction
Return
Before
Before
Before
e