A80386DX33 Intel, A80386DX33 Datasheet - Page 61

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

(6) If (RPL(CS)
(7) Resume execution of the interrupted routine The
5 FUNCTIONAL DATA
5 1 INTRODUCTION
The Intel386 DX features a straightforward function-
al interface to the external hardware The Intel386
DX has separate parallel buses for data and ad-
dress The data bus is 32-bits in width and bidirec-
tional The address bus outputs 32-bit address val-
ues in the most directly usable form for the high-
speed local bus 4 individual byte enable signals
and the 30 upper-order bits as a binary value The
data and address buses are interpreted and con-
trolled with their associated control signals
A dynamic data bus sizing feature allows the proc-
essor to handle a mix of 32- and 16-bit external bus-
es on a cycle-by-cycle basis (see 5 3 4 Data Bus
Sizing) If 16-bit bus size is selected the Intel386
DX automatically makes any adjustment needed
even performing another 16-bit bus cycle to com-
plete the transfer if that is necessary 8-bit peripheral
devices may be connected to 32-bit or 16-bit buses
with no loss of performance A new address pipe-
lining option is provided and applies to 32-bit and
16-bit buses for substantially improved memory utili-
zation especially for the most heavily used memory
resources
The address pipelining option when selected typ-
ically allows a given memory interface to operate
with one less wait state than would otherwise be
required (see 5 4 2 Address Pipelining) The pipe-
lined bus is also well suited to interleaved memory
designs When address pipelining is requested by
the external hardware the Intel386 DX will output
the address and bus cycle definition of the next bus
cycle (if it is internally available) even while waiting
for the current cycle to be acknowledged
ue of ESP stored in step 4 is used Since VM
these are done as 8086 segment register loads
Else if VM
DS FS and GS are valid in the interrupted rou-
tine Null out invalid selectors to trap if an at-
tempt is made to access through them
SS ESP from the stack The ESP register is
popped first followed by 32-bits containing SS in
the lower 16 bits If VM
protected mode segment register load If VM
an 8086 segment register load is used
VM bit in the FLAGS register (restored from the
interrupt routine’s stack image in step 1) deter-
mines whether the processor resumes the inter-
rupted routine in Protected mode of Virtual 8086
mode
e
0 check that the selectors in ES
l
CPL) pop the stack pointer
e
0 SS is loaded as a
e
e
1
1
Non-pipelined address timing however is ideal for
external cache designs since the cache memory will
typically be fast enough to allow non-pipelined cy-
cles For maximum design flexibility the address
pipelining option is selectable on a cycle-by-cycle
basis
The processor’s bus cycle is the basic mechanism
for information transfer either from system to proc-
essor or from processor to system Intel386 DX bus
cycles perform data transfer in a minimum of only
two clock periods On a 32-bit data bus the maxi-
mum Intel386 DX transfer bandwidth at 20 MHz is
therefore 40 MBytes sec at 25 MHz bandwidth is
50 Mbytes sec and at 33 MHz bandwidth is
66 Mbytes sec Any bus cycle will be extended for
more than two clock periods however if external
hardware withholds acknowledgement of the cycle
At the appropriate time acknowledgement is sig-
nalled by asserting the Intel386 DX READY
The Intel386 DX can relinquish control of its local
buses to allow mastership by other devices such as
direct memory access channels When relinquished
HLDA is the only output pin driven by the Intel386
DX providing near-complete isolation of the proces-
sor from its system The near-complete isolation
characteristic is ideal when driving the system from
test equipment and in fault-tolerant applications
Functional data covered in this chapter describes
the processor’s hardware interface First the set of
signals available at the processor pins is described
(see 5 2 Signal Description) Following that are the
signal waveforms occurring during bus cycles (see
5 3 Bus Transfer Mechanism 5 4 Bus Functional
Description and 5 5 Other Functional Descrip-
tions)
5 2 SIGNAL DESCRIPTION
5 2 1 Introduction
Ahead is a brief description of the Intel386 DX input
and output signals arranged by functional groups
Note the
cates the active or asserted state occurs when the
signal is at a low voltage When no
the signal name the signal is asserted when at the
high voltage level
Example signal M IO
Intel386
symbol at the end of a signal name indi-
TM
DX MICROPROCESSOR
High voltage indicates
Memory selected
Low
I O selected
voltage
is present after
indicates
input
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