MC68360ZP25L Freescale Semiconductor, MC68360ZP25L Datasheet - Page 509
MC68360ZP25L
Manufacturer Part Number
MC68360ZP25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360ZP25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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The HDLC event register is a memory-mapped register that may be read at any time. A bit
is cleared by writing a one (writing a zero does not affect a bit’s value). More than one bit
may be cleared at a time. All unmasked bits must be cleared before the CP will clear the
internal interrupt request. This register is cleared at reset.
Bits 15–13, 6, 5—Reserved
GLr—Glitch on Rx
RXD
CD
HDLC SCCE
NOTES:
HDLC SCCE
TXD
RTS
CTS
NOTES:
15
These bits should be written with zeros.
A clock glitch was detected by this SCC on the receive clock.
1. RXB event assumes receive buffers are 6 bytes each.
2. The second IDL event occurs after 15 ones are received in a row.
3. The FLG interrupts show the beginning and end of flag reception.
4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.
5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.
6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte.
EVENTS
1. TXB event shown assumes all three bytes were put into a single buffer.
2. Example shows one additional opening flag. This is programmable.
3. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.
EVENTS
TRANSMITTED BY HDLC
RECEIVED IN HDLC
14
—
TIME
FRAME
FRAME
13
LINE IDLE
CD
GLr
12
LINE IDLE
Figure 7-53. HDLC Interrupt Event Example
IDL
Freescale Semiconductor, Inc.
GLt
11
F
For More Information On This Product,
FLG
F
DCC
A
10
FLG
CTS
MC68360 USER’S MANUAL
A
STORED IN RX BUFFER
Go to: www.freescale.com
F
FLG
C
9
F
I
STORED IN
TX BUFFER
A
IDL
I
8
A
I
RXB
C CR CR
GRA
CR CR
7
F
Serial Communication Controllers (SCCs)
RXF
FLG
6
F
TXB
—
FLG
5
IDL
TXE
LINE IDLE
CTS
4
LINE IDLE
CD
RXF
3
BSY
2
TXB
1
RXB
0
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