MC68360ZP25L Freescale Semiconductor, MC68360ZP25L Datasheet - Page 789
MC68360ZP25L
Manufacturer Part Number
MC68360ZP25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360ZP25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
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Freescale Semiconductor, Inc.
Applications
Figure 9-23 shows an enlarged version of a device shown in Figure 9-22. The TAP is the
interface between the external bus and all internal boundary scan logic. The interface is
comprised of four mandatory signals, TDI, TDO, TCK, TMS, and the optional test reset
(TRST).
The TAP controller is a sequential state machine. The JTAG standard defines operations
that must be performed, others that should be performed, and operations that are optional
and may vary between different devices and vendors. The TAP state machine is stepped by
different combinations of the TMS and TCK signals. Data is shifted in through the TDI pin to
the instruction register, bypass register, or boundary scan register, depending on the state
machine action. The state machine also controls what internal signal path is routed to the
TDO pin.
Although the TAP details are application-specific, the discussion of how to access the TAP
controllers using the QUICC is common to all boards. This access is described in more
detail.
9-69
MC68360 USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
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