MC68360ZP25L Freescale Semiconductor, MC68360ZP25L Datasheet - Page 633
MC68360ZP25L
Manufacturer Part Number
MC68360ZP25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360ZP25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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REN—SMC Receive Enable
7.11.14.5 SMC MONITOR CHANNEL RX BD. The CP reports information about the moni-
tor channel receive byte using this BD.
E—Empty
L—Last (EOM)
ER—Error Condition
MS—Data Mismatch
Bits 11–10—Reserved
DATA—Data Field
15
When the SMC implements the monitor channel protocol, the SMC will wait until this bit
is set by the CPU32+ core before acknowledging the monitor channel data. In the trans-
parent mode, additional received data bytes will be discarded until the E-bit is set by the
CPU32+ core.
This bit is valid only when the SMC implements the monitor channel protocol. This bit is
set when the end-of-message (EOM) indication is received on the E-bit.
This bit is valid only when the SMC implements the monitor channel protocol. This bit is
set when an error condition occurs on the monitor channel protocol. (A new byte is trans-
mitted before the SMC acknowledges the previous byte.)
This bit is valid only when the SMC implements the monitor channel protocol. This bit is
set when two different consecutive bytes are received and is cleared when the last two
consecutive bytes match. The SMC waits for the reception of two identical consecutive
bytes before writing new data to the Rx BD.
These bits should be cleared by the user.
The data field contains the monitor channel data byte received by the SMC.
E
0 = SMC receiver disabled
1 = SMC receiver enabled
0 = This bit is cleared by the CP to indicate that data byte associated with this BD is
1 = This bit is set by the CPU32+ core to indicate that the data byte associated with
14
L
now available to the CPU32+ core.
this BD has been read.
ER
13
When this bit is set, the data byte is not valid.
MS
12
Freescale Semiconductor, Inc.
11
For More Information On This Product,
—
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
—
9
—
NOTE
8
7
6
Serial Management Controllers (SMCs)
5
4
DATA
3
2
1
0
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