FW80200M733SL678 Intel, FW80200M733SL678 Datasheet - Page 11

• Manufacturer Part Number: FW80200M733SL678
• Description: IC I/O PROCESSOR 733MHZ 241-BGA
• Manufacturer: Intel

Specifications of FW80200M733SL678

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-BGA
• Other names: 844850

Datasheet - Commercial and Extended Temperature (80200T)
2.8
2.9
2.10
Fill Buffer (FB) and Pend Buffer (PB)
The 4-entry Fill Buffer works with the core to hold loads until the bus controller can act on them.
The FB and the 4-entry Pend Buffer work with the d-cache and mini-data cache to provide
“hit-under-miss” capability, allowing the core to seek other data in the caches while “miss” data is
being fetched from memory. The FB can contain up to four unique “miss” addresses (logical),
allowing four “misses” before the core is stalled. The PB holds up to four addresses (logical) for
additional “misses” to those addresses that are already in the FB. A coprocessor register can
specify draining of the Fill and Pend (Write) Buffers.
Write Buffer (WB)
The Write Buffer holds data for storage to memory until the bus controller can act on it. The WB is
8-entries deep, where each entry holds 16 bytes. The WB is constantly enabled, and accepts data
from the core, d-cache, or mini-data cache.
Coprocessor 15, register 1 specifies whether WB coalescing is enabled or disabled. When
coalescing is disabled, stores to memory occur in program order regardless of the attribute bits
within the descriptors located in the DTLB. When coalescing is enabled, the attribute bits within
the descriptors located in the DTLB are examined to determine when coalescing is enabled for the
destination region of memory. When coalescing is enabled in both CP15, R1 and the DTLB, then
data entering the WB can coalesce with any of the 8-entries (16 bytes) and then be stored to the
destination memory region, but possibly out of program order.
Stores to a memory region specified to be non-cacheable and non-bufferable by the attribute bits
within the descriptors located in the DTLB causes the Core to stall until the store completes. A
coprocessor register can specify draining of the write buffer.
Multiply-Accumulate Coprocessor (CP0)
For efficient processing of high-quality audio algorithms, CP0 provides 40-bit accumulation of
16x16, dual-16x16 (SIMD), and 32x32 signed multiplies. Special MAR and MRA instructions are
implemented to Move 40-bit Accumulator to Two Core General Registers (MAR) and Move Two
Core General Registers to 40-bit Accumulator (MRA). The 40-bit accumulator can be stored or
loaded to or from d-cache, mini-data cache, or memory using two STC or LDC instructions.
16x16 signed multiply-accumulates (MIAxy) multiply either the high/high, low/low, high/low, or
low/high 16 bits of a 32-bit core general register (multiplier) and another 32-bit core general
register (multiplicand) to produce a full 32-bit product which is sign-extended to 40 bits and then
added to the 40-bit accumulator.
Dual signed 16x16 (SIMD) multiply-accumulates (MIAPH) multiply the high/high and low/low
16-bits of a packed 32-bit core general register (multiplier) and another packed 32-bit core general
register (multiplicand) to produce two 16-bits products which are both sign-extended to 40 bits and
then both added to the 40-bit accumulator.
32x32 signed multiply-accumulates (MIA) multiply a 32-bit core general register (multiplier) and
another 32-bit core general register (multiplicand) to produce a 64-bit product where the 40 LSBs
are added to the 40-bit accumulator. 16x32 versions of the multiply-accumulate instructions
complete in a single cycle.
Intel
®
80200 Processor based on Intel
January 2003
®
XScale
Functional Overview
™
Microarchitecture
11