FW80200M733SL678 Intel, FW80200M733SL678 Datasheet - Page 9

• Manufacturer Part Number: FW80200M733SL678
• Description: IC I/O PROCESSOR 733MHZ 241-BGA
• Manufacturer: Intel

Specifications of FW80200M733SL678

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-BGA
• Other names: 844850

Datasheet - Commercial and Extended Temperature (80200T)
2.4
2.5
Data Memory Management Unit (DMMU)
For data fetches, the DMMU controls logical-to-physical address translation, memory access
permissions, memory domain identifications, and attributes (governing operation of the data cache
or mini-data cache and write buffer). The DMMU contains a 32-entry, fully associative data
translation look-a-side buffer (DTLB) that has a round-robin replacement policy. DTLB entries
0-30 can be locked.
When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk mechanism
that fetches an associated descriptor from memory and loads it into the DTLB. The descriptor
contains information for logical-to-physical address translation, memory access permissions,
memory domain identifications, and attributes (governing operation of the d-cache or mini-data
cache and write buffer). The DMMU then continues the data fetch by using the address translation
just entered into the DTLB. When a data fetch hits in the DTLB, the DMMU continues the fetch
using the address translation already resident in the DTLB.
Access permissions for each of up to sixteen memory domains can be programmed. When a data
fetch is attempted to an area of memory in violation of access permissions, then the attempt is
aborted and a data abort is sent to the core for exception processing. The IMMU and DMMU can
be enable or disable together.
Instruction Cache (I-Cache)
The I-Cache can contain high-use multiple code segments or entire programs, allowing the core
access to instructions at core frequencies. This prevents core stalls caused by multicycle accesses to
external memory.
The 32 KByte i-cache is 32-set/32-way associative, where each set contains 32-ways and each way
contains a tag address, a cache line (eight 32-bit words and one parity bit per word) of instructions,
and a line-valid bit. For each of the 32 sets, 0-28 ways can be locked. Unlocked ways are
replaceable via a round robin policy.
The i-cache can be enabled or disabled. Attribute bits within the descriptors contained in the ITLB
of the IMMU provide some control over an enabled i-cache.
When a needed line (eight 32-bit words) is not present in the i-cache, the line is fetched (critical
word first) from memory via a two-level-deep fetch queue.
Intel
®
80200 Processor based on Intel
January 2003
®
XScale
Functional Overview
™
Microarchitecture
9