FW80200M733SL678 Intel, FW80200M733SL678 Datasheet - Page 7

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FW80200M733SL678

Manufacturer Part Number
FW80200M733SL678
Description
IC I/O PROCESSOR 733MHZ 241-BGA
Manufacturer
Intel
Datasheet

Specifications of FW80200M733SL678

Rohs Status
RoHS non-compliant
Processor Type
I/O
Features
XScale Core
Speed
733MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-BGA
Other names
844850

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Datasheet - Commercial and Extended Temperature (80200T)
2.1
Superpipeline
The Superpipeline is composed of Integer, Multiply-Accumulate (MAC), and memory pipes.
The Integer pipe has seven stages:
The Memory pipe has eight stages:
. . . then finish with Memory stages:
The MAC pipe has six to nine stages:
. . . then finish with MAC stages:
The MAC pipe supports a data-dependent early terminate where stages MAC2, MAC3, and/or
MAC4 are by-passed.
Deep pipes promote high instruction execution rates only when a means exists to successfully
predict the outcome of branch instructions. The Branch Target Buffer provides such a means.
Branch Target Buffer (BTB)/Fetch 1
Fetch 2
Decode
Register File/Shift
ALU Execute
State Execute
Integer Writeback
the first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)
Data Cache 1
Data Cache 2
Data Cache Writeback
the first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift)
MAC1
MAC2
MAC3
MAC4
Register Writeback
Intel
®
80200 Processor based on Intel
January 2003
®
XScale
Functional Overview
Microarchitecture
7

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